PIC17C7XX_13 Datasheet, PDF (110/306 Pages) Microchip Technology – High-Performance 8-bit CMOS EPROM Microcontrollers with 10-bit A/D

PIC17C7XX
13.2 Timer3
Timer3 is a 16-bit timer consisting of the TMR3H and
TMR3L registers. TMR3H is the high byte of the timer
and TMR3L is the low byte. This timer has an associ-
ated 16-bit period register (PR3H/CA1H:PR3L/CA1L).
This period register can be software configured to be a
another 16-bit capture register.
When the TMR3CS bit (TCON1<2>) is clear, the timer
increments every instruction cycle (FOSC/4). When
TMR3CS is set, the counter increments on every falling
edge of the RB5/TCLK3 pin. In either mode, the
TMR3ON bit must be set for the timer/counter to incre-
ment. When TMR3ON is clear, the timer will not incre-
ment or set flag bit TMR3IF.
Timer3 has two modes of operation, depending on the
CA1/PR3 bit (TCON2<3>). These modes are:
• Three capture and one period register mode
• Four capture register mode
The PIC17C7XX has up to four 16-bit capture registers
that capture the 16-bit value of TMR3 when events are
detected on capture pins. There are four capture pins
(RB0/CAP1, RB1/CAP2, RG4/CAP3, and RE3/CAP4),
one for each capture register pair. The capture pins are
multiplexed with the I/O pins. An event can be:
• A rising edge
• A falling edge
• Every 4th rising edge
• Every 16th rising edge
Each 16-bit capture register has an interrupt flag asso-
ciated with it. The flag is set when a capture is made.
The capture modules are truly part of the Timer3 block.
Figure 13-5 and Figure 13-6 show the block diagrams
for the two modes of operation.
13.2.1 THREE CAPTURE AND ONE
PERIOD REGISTER MODE
In this mode, registers PR3H/CA1H and PR3L/CA1L
constitute a 16-bit period register. A block diagram is
shown in Figure 13-5. The timer increments until it
equals the period register and then resets to 0000h on
the next timer clock. TMR3 Interrupt Flag bit (TMR3IF)
is set at this point. This interrupt can be disabled by
clearing the TMR3 Interrupt Enable bit (TMR3IE).
TMR3IF must be cleared in software.
FIGURE 13-5:
RB5/TCLK3
TIMER3 WITH THREE CAPTURE AND ONE PERIOD REGISTER BLOCK DIAGRAM
TMR3CS
(TCON1<2>)
FOSC/4
0
1
TMR3ON
(TCON2<2>)
PR3H/CA1H PR3L/CA1L
Comparator<x81>6
TMR3H
TMR3L
Equal
Reset
Set TMR3IF
(PIR1<6>)
RB1/CAP2
RG4/CAP3
Edge select,
Prescaler select
Capture2
Enable
2
CA2ED1: CA2ED0
(TCON1<7:6>)
Edge select,
Prescaler select
CA2H
Set CA2IF
(PIR1<3>)
Capture3
Enable
2
CA3ED1: CA3ED0
(TCON3<2:1>)
CA3H
Set CA3IF
(PIR2<2>)
CA2L
CA3L
RE3/CAP4
Edge select,
Prescaler select
Capture4
Enable
2
CA4ED1: CA4ED0
(TCON3<4:3>)
CA4H
Set CA4IF
(PIR2<3>)
CA4L
DS30289C-page 110
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