PIC17C7XX_13 Datasheet, PDF (201/306 Pages) Microchip Technology – High-Performance 8-bit CMOS EPROM Microcontrollers with 10-bit A/D

PIC17C7XX
TABLE 18-2: PIC17CXXX INSTRUCTION SET (CONTINUED)
Mnemonic,
Operands
Description
Cycles
16-bit Opcode
MSb
LSb
Status
Affected
Notes
TSTFSZ f
Test f, skip if 0
XORWF f,d
Exclusive OR WREG with f
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
f,b
Bit Clear f
BSF
f,b
Bit Set f
BTFSC f,b
Bit test, skip if clear
BTFSS f,b
Bit test, skip if set
BTG
f,b
Bit Toggle f
LITERAL AND CONTROL OPERATIONS
ADDLW k
ADD literal to WREG
ANDLW k
AND literal with WREG
CALL
k
Subroutine Call
1 (2) 0011 0011 ffff ffff
None
6,8
1 0000 110d ffff ffff
Z
1 1000 1bbb ffff ffff
None
1 1000 0bbb ffff ffff
None
1 (2) 1001 1bbb ffff ffff
None
6,8
1 (2) 1001 0bbb ffff ffff
None
6,8
1 0011 1bbb ffff ffff
None
1 1011 0001 kkkk kkkk OV,C,DC,Z
1 1011 0101 kkkk kkkk
Z
2 111k kkkk kkkk kkkk
None
7
CLRWDT —
GOTO k
IORLW k
LCALL k
MOVLB k
MOVLR k
MOVLW k
MULLW k
RETFIE —
RETLW k
RETURN —
Clear Watchdog Timer
Unconditional Branch
Inclusive OR literal with WREG
Long Call
Move literal to low nibble in BSR
Move literal to high nibble in BSR
Move literal to WREG
Multiply literal with WREG
Return from interrupt (and enable interrupts)
Return literal to WREG
Return from subroutine
1 0000 0000 0000 0100 TO, PD
2 110k kkkk kkkk kkkk
None
7
1 1011 0011 kkkk kkkk
Z
2 1011 0111 kkkk kkkk
None
4,7
1 1011 1000 uuuu kkkk
None
1 1011 101x kkkk uuuu
None
1 1011 0000 kkkk kkkk
None
1 1011 1100 kkkk kkkk
None
2 0000 0000 0000 0101 GLINTD
7
2 1011 0110 kkkk kkkk
None
7
2 0000 0000 0000 0010
None
7
SLEEP —
Enter SLEEP mode
1 0000 0000 0000 0011 TO, PD
SUBLW k
Subtract WREG from literal
1 1011 0010 kkkk kkkk OV,C,DC,Z
XORLW k
Exclusive OR literal with WREG
1 1011 0100 kkkk kkkk
Z
Legend: Refer to Table 18-1 for opcode field descriptions.
Note 1: 2’s Complement method.
2: Unsigned arithmetic.
3: If s = '1', only the file is affected: If s = '0', both the WREG register and the file are affected; If only the Working register
(WREG) is required to be affected, then f = WREG must be specified.
4: During an LCALL, the contents of PCLATH are loaded into the MSB of the PC and kkkk kkkk is loaded into the LSB of the
PC (PCL).
5: Multiple cycle instruction for EPROM programming when table pointer selects internal EPROM. The instruction is termi-
nated by an interrupt event. When writing to external program memory, it is a two-cycle instruction.
6: Two-cycle instruction when condition is true, else single cycle instruction.
7: Two-cycle instruction except for TABLRD to PCL (program counter low byte), in which case it takes 3 cycles.
8: A “skip” means that instruction fetched during execution of current instruction is not executed, instead a NOP is executed.
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DS30289C-page 201