PIC17C7XX_13 Datasheet, PDF (183/306 Pages) Microchip Technology – High-Performance 8-bit CMOS EPROM Microcontrollers with 10-bit A/D

16.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 16-3. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance varies over the device voltage
(VDD), Figure 16-3. The maximum recommended
impedance for analog sources is 10 k. As the
impedance is decreased, the acquisition time may be
decreased. After the analog input channel is selected
(changed) this acquisition must be done before the
conversion can be started.
EQUATION 16-1: ACQUISITION TIME
TACQ =
=
Amplifier Settling Time +
Holding Capacitor Charging Time +
Temperature Coefficient
TAMP + TC + TCOFF
PIC17C7XX
To calculate the minimum acquisition time,
Equation 16-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
Example 16-1 shows the calculation of the minimum
required acquisition time (TACQ). This is based on the
following application system assumptions.
CHOLD
Rs
Conversion Error
VDD
Temperature
VHOLD
= 120 pF
= 10 k
 1/2 LSb
= 5V  Rss = 7 k
(see graph in Figure 16-3)
= 50C (system max.)
= 0V @ time = 0
EQUATION 16-2: A/D MINIMUM CHARGING TIME
VHOLD
or
TC
= (VREF - (VREF/2048)) • (1 - e^{(-Tc/CHOLD(RIC + RSS + RS))})
= -(120 pF)(1 k + RSS + RS) ln(1/2047)
EXAMPLE 16-1: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
TACQ = TAMP + TC + TCOFF
Temperature coefficient is only required for temperatures > 25C.
TACQ =
2 s + Tc + [(Temp - 25C)(0.05 s/C)]
TC =
-CHOLD (RIC + RSS + RS) ln(1/2047)
-120 pF (1 k + 7 k + 10 k) ln(0.0004885)
-120 pF (18 k) ln(0.0004885)
-2.16 s (-7.6241)
16.47 s
TACQ =
2 s + 16.47 s + [(50×C - 25C)(0.05 sC)]
18.447 s + 1.25 s
19.72 s
Note 1: The reference voltage (VREF) has no effect on the equation since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
4: After a conversion has completed, a 2.0 TAD delay must complete before acquisition can begin again.
During this time, the holding capacitor is not connected to the selected A/D input channel.
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DS30289C-page 183