PIC17C7XX_13 Datasheet, PDF (221/306 Pages) Microchip Technology – High-Performance 8-bit CMOS EPROM Microcontrollers with 10-bit A/D

PIC17C7XX
RETFIE
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
No
operation
Return from Interrupt
[ label ] RETFIE
None
TOS  (PC);
0  GLINTD;
PCLATH is unchanged.
GLINTD
0000 0000 0000 0101
Return from Interrupt. Stack is POP’ed
and Top-of-Stack (TOS) is loaded in the
PC. Interrupts are enabled by clearing
the GLINTD bit. GLINTD is the global
interrupt disable bit (CPUSTA<4>).
1
2
Q2
No
operation
No
operation
Q3
Clear
GLINTD
No
operation
Q4
POP PC
from stack
No
operation
Example:
RETFIE
After Interrupt
PC
= TOS
GLINTD = 0
RETLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
No
operation
Return Literal to WREG
[ label ] RETLW k
0  k  255
k  (WREG); TOS  (PC);
PCLATH is unchanged
None
1011 0110 kkkk kkkk
WREG is loaded with the eight-bit literal
'k'. The program counter is loaded from
the top of the stack (the return address).
The high address latch (PCLATH)
remains unchanged.
1
2
Q2
Read
literal 'k'
No
operation
Q3
Process
Data
No
operation
Q4
POP PC
from stack,
Write to
WREG
No
operation
Example:
CALL TABLE ; WREG contains table
; offset value
; WREG now has
; table value
:
TABLE
ADDWF PC ; WREG = offset
RETLW k0 ; Begin table
RETLW k1 ;
:
:
RETLW kn ; End of table
Before Instruction
WREG = 0x07
After Instruction
WREG = value of k7
 1998-2013 Microchip Technology Inc.
DS30289C-page 221