PIC17C7XX_13 Datasheet, PDF (136/306 Pages) Microchip Technology – High-Performance 8-bit CMOS EPROM Microcontrollers with 10-bit A/D

PIC17C7XX
REGISTER 15-3: SSPCON2: SYNC SERIAL PORT CONTROL REGISTER2 (ADDRESS 12h, BANK 6)
R/W-0
GCEN
bit 7
R/W-0
R/W-0
ACKSTAT ACKDT
R/W-0
ACKEN
R/W-0
RCEN
R/W-0
PEN
R/W-0
RSEN
R/W-0
SEN
bit 0
bit 7
GCEN: General Call Enable bit (in I²C Slave mode only)
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR
0 = General call address disabled
bit 6
ACKSTAT: Acknowledge Status bit (in I²C Master mode only)
In Master Transmit mode:
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
bit 5
ACKDT: Acknowledge Data bit (in I²C Master mode only)
In Master Receive mode:
Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a
receive.
1 = Not Acknowledge
0 = Acknowledge
bit 4
ACKEN: Acknowledge Sequence Enable bit (in I²C Master mode only)
In Master Receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins and transmit AKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence idle
Note: If the I²C module is not in the IDLE mode, this bit may not be set (no spooling) and
the SSPBUF may not be written (or writes to the SSPBUF are disabled).
bit 3
RCEN: Receive Enable bit (in I²C Master mode only)
1 = Enables Receive mode for I²C
0 = Receive idle
Note: If the I²C module is not in the IDLE mode, this bit may not be set (no spooling) and
the SSPBUF may not be written (or writes to the SSPBUF are disabled).
bit 2
PEN: STOP Condition Enable bit (in I²C Master mode only)
SCK Release Control:
1 = Initiate STOP condition on SDA and SCL pins. Automatically cleared by hardware.
0 = STOP condition idle
Note: If the I²C module is not in the IDLE mode, this bit may not be set (no spooling) and
the SSPBUF may not be written (or writes to the SSPBUF are disabled).
bit 1
RSEN: Repeated Start Condition Enabled bit (in I²C Master mode only)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition idle
Note: If the I²C module is not in the IDLE mode, this bit may not be set (no spooling) and
the SSPBUF may not be written (or writes to the SSPBUF are disabled).
bit 0
SEN: START Condition Enabled bit (In I²C Master mode only)
1 = Initiate START condition on SDA and SCL pins. Automatically cleared by hardware.
0 = START condition idle.
Note: If the I²C module is not in the IDLE mode, this bit may not be set (no spooling) and
the SSPBUF may not be written (or writes to the SSPBUF are disabled).
Legend:
R = Readable bit
- n = Value at POR Reset
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
DS30289C-page 136
 1998-2013 Microchip Technology Inc.