PIC17C7XX_13 Datasheet, PDF (259/306 Pages) Microchip Technology – High-Performance 8-bit CMOS EPROM Microcontrollers with 10-bit A/D

PIC17C7XX
FIGURE 20-18: I²C BUS DATA TIMING
103
100
101
SCL
SDA
In
90
91
106
107
109
109
SDA
Out
Note: Refer to Figure 20-5 for load conditions.
102
92
110
TABLE 20-13: I²C BUS DATA REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Max Units
Conditions
100 Thigh Clock high time
100 kHz mode 2(TOSC)(BRG + 1) —
ms
400 kHz mode 2(TOSC)(BRG + 1) —
ms
1 MHz mode⁽¹⁾ 2(TOSC)(BRG + 1)
—
ms
101 Tlow Clock low time
100 kHz mode 2(TOSC)(BRG + 1) —
ms
400 kHz mode 2(TOSC)(BRG + 1) —
ms
1 MHz mode⁽¹⁾ 2(TOSC)(BRG + 1)
—
ms
102
Tr SDA and SCL rise time 100 kHz mode
400 kHz mode
1 MHz mode⁽¹⁾
—
20 + 0.1Cb
—
1000
300
300
ns Cb is specified to be from
ns ^{10 to 400 pF}
ns
103
Tf SDA and SCL fall time 100 kHz mode
400 kHz mode
1 MHz mode⁽¹⁾
—
20 + 0.1Cb
—
300
ns Cb is specified to be from
300
ns ^{10 to 400 pF}
10
ns
90 Tsu:sta START condition setup 100 kHz mode 2(TOSC)(BRG + 1) —
time
400 kHz mode 2(TOSC)(BRG + 1) —
1 MHz mode⁽¹⁾ 2(TOSC)(BRG + 1)
—
ms Only relevant for Repeated
ms ^{Start condition}
ms
91 Thd:sta START condition hold 100 kHz mode 2(TOSC)(BRG + 1) —
time
400 kHz mode 2(TOSC)(BRG + 1) —
1 MHz mode⁽¹⁾ 2(TOSC)(BRG + 1)
—
ms After this period, the first
ms ^{clock pulse is generated}
ms
106 Thd:dat Data input hold time 100 kHz mode
0
—
ns
400 kHz mode
0
0.9
ms
1 MHz mode⁽¹⁾
0
—
ns
107 Tsu:dat Data input setup time 100 kHz mode
250
—
ns (Note 2)
400 kHz mode
100
1 MHz mode⁽¹⁾
100
—
ns
—
ns
92 Tsu:sto STOP condition
setup time
100 kHz mode 2(TOSC)(BRG + 1) —
ms
400 kHz mode 2(TOSC)(BRG + 1) —
ms
1 MHz mode⁽¹⁾ 2(TOSC)(BRG + 1)
—
ms
109
Taa Output valid from clock 100 kHz mode
—
3500 ns
400 kHz mode
—
1000 ns
1 MHz mode⁽¹⁾
—
400
ns
Note 1: Maximum pin capacitance = 10 pF for all I²C pins.
2: A fast mode (400 KHz) I²C bus device can be used in a standard mode I²C bus system, but the parameter # 107  250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If
such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line.
Parameter #102 + #107 = 1000 + 250 = 1250 ns (for 100 kHz mode) before the SCL line is released.
3: C_b is specified to be from 10-400pF. The minimum specifications are characterized with C_b=10pF. The rise time spec (t_r)
is characterized with R_p=R_p min. The minimum fall time specification (t_f) is characterized with C_b=10pF,and R_p=R_p max.
These are only valid for fast mode operation (VDD=4.5-5.5V) and where the SPM bit (SSPSTAT<7>) =1.)
4: Max specifications for these parameters are valid for falling edge only. Specs are characterized with R_p=R_p min and
C_b=400pF for standard mode, 200pF for fast mode, and 10pF for 1MHz mode.
 1998-2013 Microchip Technology Inc.
DS30289C-page 259