PIC17C7XX_13 Datasheet, PDF (123/306 Pages) Microchip Technology – High-Performance 8-bit CMOS EPROM Microcontrollers with 10-bit A/D

PIC17C7XX
14.2 USART Asynchronous Mode
In this mode, the USART uses standard nonreturn-to-
zero (NRZ) format (one START bit, eight or nine data
bits, and one STOP bit). The most common data format
is 8-bits. An on-chip dedicated 8-bit baud rate genera-
tor can be used to derive standard baud rate frequen-
cies from the oscillator. The USART’s transmitter and
receiver are functionally independent but use the same
data format and baud rate. The baud rate generator
produces a clock x64 of the bit shift rate. Parity is not
supported by the hardware, but can be implemented in
software (and stored as the ninth data bit). Asynchro-
nous mode is stopped during SLEEP.
The Asynchronous mode is selected by clearing the
SYNC bit (TXSTA<4>).
The USART Asynchronous module consists of the fol-
lowing components:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
14.2.1 USART ASYNCHRONOUS
TRANSMITTER
The USART transmitter block diagram is shown in
Figure 14-1. The heart of the transmitter is the transmit
shift register (TSR). The shift register obtains its data
from the read/write transmit buffer (TXREG). TXREG is
loaded with data in software. The TSR is not loaded until
the STOP bit has been transmitted from the previous
load. As soon as the STOP bit is transmitted, the TSR is
loaded with new data from the TXREG (if available).
Once TXREG transfers the data to the TSR (occurs in
one TCY at the end of the current BRG cycle), the TXREG
is empty and an interrupt bit, TXIF, is set. This interrupt
can be enabled/disabled by setting/clearing the TXIE bit.
TXIF will be set, regardless of TXIE and cannot be reset
in software. It will reset only when new data is loaded into
TXREG. While TXIF indicates the status of the TXREG,
the TRMT (TXSTA<1>) bit shows the status of the TSR.
TRMT is a read only bit which is set when the TSR is
empty. No interrupt logic is tied to this bit, so the user has
to poll this bit in order to determine if the TSR is empty.
Note: The TSR is not mapped in data memory,
so it is not available to the user.
Transmission is enabled by setting the
TXEN (TXSTA<5>) bit. The actual transmission will not
occur until TXREG has been loaded with data and the
baud rate generator (BRG) has produced a shift clock
(Figure 14-3). The transmission can also be started by
first loading TXREG and then setting TXEN. Normally,
when transmission is first started, the TSR is empty, so
a transfer to TXREG will result in an immediate transfer
to TSR, resulting in an empty TXREG. A back-to-back
transfer is thus possible (Figure 14-4). Clearing TXEN
during a transmission will cause the transmission to be
aborted. This will reset the transmitter and the TX/CK
pin will revert to hi-impedance.
In order to select 9-bit transmission, the
TX9 (TXSTA<6>) bit should be set and the ninth bit
value should be written to TX9D (TXSTA<0>). The
ninth bit value must be written before writing the 8-bit
data to the TXREG. This is because a data write to
TXREG can result in an immediate transfer of the data
to the TSR (if the TSR is empty).
Steps to follow when setting up an Asynchronous
Transmission:
1. Initialize the SPBRG register for the appropriate
baud rate.
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
3. If interrupts are desired, then set the TXIE bit.
4. If 9-bit transmission is desired, then set the TX9
bit.
5. If 9-bit transmission is selected, the ninth bit
should be loaded in TX9D.
6. Load data to the TXREG register.
7. Enable the transmission by setting TXEN (starts
transmission).
FIGURE 14-3:
ASYNCHRONOUS MASTER TRANSMISSION
Write to TXREG
BRG Output
(Shift Clock)
TX
(TX/CK pin)
TXIF bit
Word 1
START Bit
Bit 0
Bit 1
Word 1
Bit 7/8 _{STOP Bit}
TRMT bit
Word 1
Transmit Shift Reg
 1998-2013 Microchip Technology Inc.
DS30289C-page 123