PIC17C7XX_13 Datasheet, PDF (167/306 Pages) Microchip Technology – High-Performance 8-bit CMOS EPROM Microcontrollers with 10-bit A/D

PIC17C7XX
15.2.14 STOP CONDITION TIMING
A STOP bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit PEN (SSPCON2<2>). At the end of a receive/
transmit the SCL line is held low after the falling edge
of the ninth clock. When the PEN bit is set, the master
will assert the SDA line low. When the SDA line is sam-
pled low, the baud rate generator is reloaded and
counts down to ‘0’. When the baud rate generator times
out, the SCL pin will be brought high and one TBRG
(baud rate generator rollover count) later, the SDA pin
will be de-asserted. When the SDA pin is sampled high
while SCL is high, the P bit (SSPSTAT<4>) is set. A
TBRG later, the PEN bit is cleared and the SSPIF bit is
set (Figure 15-31).
Whenever the firmware decides to take control of the
bus, it will first determine if the bus is busy by checking
the S and P bits in the SSPSTAT register. If the bus is
busy, then the CPU can be interrupted (notified) when
a STOP bit is detected (i.e., bus is free).
15.2.14.1 WCOL Status Flag
If the user writes the SSPBUF when a STOP sequence
is in progress, then WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
FIGURE 15-31: STOP CONDITION RECEIVE OR TRANSMIT MODE
Write to SSPCON2
Set PEN
Falling Edge of
9th Clock
SCL
TBRG
SCL = 1 for TBRG, followed by SDA = 1 for TBRG
after SDA sampled high. P bit (SSPSTAT<4>) is set.
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set.
SDA
ACK
TBRG
P
TBRG
TBRG
SCL brought high after TBRG.
SDA asserted low before rising edge of clock
to setup STOP condition.
Note: TBRG = one baud rate generator period.
 1998-2013 Microchip Technology Inc.
DS30289C-page 167