PIC17C7XX_13 Datasheet, PDF (255/306 Pages) Microchip Technology – High-Performance 8-bit CMOS EPROM Microcontrollers with 10-bit A/D

PIC17C7XX
FIGURE 20-14: SPI MASTER MODE TIMING (CKE = 1)
SS
81
SCK
(CKP = 0)
71
72
79
73
SCK
(CKP = 1)
80
78
SDO
MSb
BIT6 - - - - - -1
75, 76
SDI
MSb IN
BIT6 - - - -1
Note:
74
Refer to Figure 20-5 for load conditions.
LSb
LSb IN
TABLE 20-9: SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param.
No.
Symbol
Characteristic
Min
71 TscH
71A
SCK input high time
(Slave mode)
Continuous
Single Byte
1.25TCY + 30
40
72 TscL
72A
SCK input low time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30
40
73 TdiV2scH, Setup time of SDI data input to SCK edge
100
TdiV2scL
73A TB2B
Last clock edge of Byte1 to the 1st clock edge
of Byte2
1.5TCY + 40
74 TscH2diL, Hold time of SDI data input to SCK edge
100
TscL2diL
75 TdoR
SDO data output rise time
—
76 TdoF
SDO data output fall time
—
78 TscR
SCK output rise time (Master mode)
—
79 TscF
SCK output fall time (Master mode)
—
80 TscH2doV, SDO data output valid after SCK edge
—
TscL2doV
81 TdoV2scH, SDO data output setup to SCK edge
Tcy
TdoV2scL
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
Typ† Max Units Conditions
— — ns
— — ns (Note 1)
— — ns
— — ns (Note 1)
— — ns
— — ns (Note 1)
— — ns
10 25 ns
10 25 ns
10 25 ns
10 25 ns
— 50 ns
— — ns
 1998-2013 Microchip Technology Inc.
DS30289C-page 255