PIC17C7XX_13 Datasheet, PDF (214/306 Pages) Microchip Technology – High-Performance 8-bit CMOS EPROM Microcontrollers with 10-bit A/D

PIC17C7XX
INFSNZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Increment f, skip if not 0
[label] INFSNZ f,d
0  f  255
d  [0,1]
(f) + 1  (dest),
skip if not 0
None
0010 010d ffff ffff
The contents of register 'f' are incre-
mented. If 'd' is 0, the result is placed in
WREG. If 'd' is 1, the result is placed
back in register 'f'.
If the result is not 0, the next instruction,
which is already fetched is discarded
and a NOP is executed instead, making
it a two-cycle instruction.
1
1(2)
Q2
Read
register 'f'
Q3
Process
Data
Q4
Write to
destination
If skip:
Q1
No
operation
Q2
No
operation
Q3
No
operation
Q4
No
operation
Example:
HERE
ZERO
NZERO
INFSNZ REG, 1
Before Instruction
REG = REG
After Instruction
REG =
If REG =
PC =
If REG =
PC =
REG + 1
1;
Address (ZERO)
0;
Address (NZERO)
IORLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Inclusive OR Literal with WREG
[ label ] IORLW k
0  k  255
(WREG) .OR. (k)  (WREG)
Z
1011 0011 kkkk kkkk
The contents of WREG are OR’ed with
the eight-bit literal 'k'. The result is
placed in WREG.
1
1
Q2
Read
literal 'k'
Q3
Process
Data
Q4
Write to
WREG
Example:
IORLW
Before Instruction
WREG = 0x9A
After Instruction
WREG = 0xBF
0x35
DS30289C-page 214
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