PIC17C7XX_13 Datasheet, PDF (35/306 Pages) Microchip Technology – High-Performance 8-bit CMOS EPROM Microcontrollers with 10-bit A/D

PIC17C7XX
6.2 Peripheral Interrupt Enable
Register1 (PIE1) and Register2
(PIE2)
These registers contains the individual enable bits for
the peripheral interrupts.
REGISTER 6-2: PIE1 REGISTER (ADDRESS: 17h, BANK 1)
R/W-0
RBIE
bit 7
R/W-0
TMR3IE
R/W-0
TMR2IE
R/W-0
TMR1IE
R/W-0
CA2IE
R/W-0
CA1IE
R/W-0
TX1IE
R/W-0
RC1IE
bit 0
bit 7
RBIE: PORTB Interrupt-on-Change Enable bit
1 = Enable PORTB interrupt-on-change
0 = Disable PORTB interrupt-on-change
bit 6
TMR3IE: TMR3 Interrupt Enable bit
1 = Enable TMR3 interrupt
0 = Disable TMR3 interrupt
bit 5
TMR2IE: TMR2 Interrupt Enable bit
1 = Enable TMR2 interrupt
0 = Disable TMR2 interrupt
bit 4
TMR1IE: TMR1 Interrupt Enable bit
1 = Enable TMR1 interrupt
0 = Disable TMR1 interrupt
bit 3
CA2IE: Capture2 Interrupt Enable bit
1 = Enable Capture2 interrupt
0 = Disable Capture2 interrupt
bit 2
CA1IE: Capture1 Interrupt Enable bit
1 = Enable Capture1 interrupt
0 = Disable Capture1 interrupt
bit 1
TX1IE: USART1 Transmit Interrupt Enable bit
1 = Enable USART1 Transmit buffer empty interrupt
0 = Disable USART1 Transmit buffer empty interrupt
bit 0
RC1IE: USART1 Receive Interrupt Enable bit
1 = Enable USART1 Receive buffer full interrupt
0 = Disable USART1 Receive buffer full interrupt
Legend:
R = Readable bit
- n = Value at POR Reset
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
 1998-2013 Microchip Technology Inc.
DS30289C-page 35