PIC17C7XX_13 Datasheet, PDF (151/306 Pages) Microchip Technology – High-Performance 8-bit CMOS EPROM Microcontrollers with 10-bit A/D

PIC17C7XX
15.2.5 MASTER MODE
Master mode of operation is supported by interrupt
generation on the detection of the START and STOP
conditions. The STOP (P) and START (S) bits are
cleared from a RESET, or when the MSSP module is
disabled. Control of the I²C bus may be taken when the
P bit is set, or the bus is idle, with both the S and P bits
clear.
In Master mode, the SCL and SDA lines are manipu-
lated by the MSSP hardware.
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt if enabled):
• START condition
• STOP condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated Start
FIGURE 15-17: SSP BLOCK DIAGRAM (I²C MASTER MODE)
SDA
SDA In
Read
Internal
Data Bus
Write
SSPBUF
SSPSR
MSb
Shift
Clock
LSb
SSPM3:SSPM0
SSPADD<6:0>
Baud
Rate
Generator
SCL
START bit, STOP bit,
Acknowledge
Generate
SCL In
Bus Collision
START bit Detect,
STOP bit Detect
Write Collision Detect
Clock Arbitration
State Counter for
end of XMIT/RCV
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
 1998-2013 Microchip Technology Inc.
DS30289C-page 151