PIC17C7XX_13 Datasheet, PDF (146/306 Pages) Microchip Technology – High-Performance 8-bit CMOS EPROM Microcontrollers with 10-bit A/D

PIC17C7XX
15.2.1.3 Slave Transmission
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit, and the SCL pin is held low.
The transmit data must be loaded into the SSPBUF
register, which also loads the SSPSR register. Then
SCL pin should be enabled by setting bit CKP
(SSPCON1<4>). The master must monitor the SCL pin
prior to asserting another clock pulse. The slave
devices may be holding off the master by stretching the
clock. The eight data bits are shifted out on the falling
edge of the SCL input. This ensures that the SDA sig-
nal is valid during the SCL high time (Figure 15-13).
An SSP interrupt is generated for each data transfer
byte. The SSPIF flag bit must be cleared in software,
and the SSPSTAT register is used to determine the sta-
tus of the byte transfer. The SSPIF flag bit is set on the
falling edge of the ninth clock pulse.
As a slave-transmitter, the ACK pulse from the master-
receiver is latched on the rising edge of the ninth SCL
input pulse. If the SDA line was high (not ACK), then
the data transfer is complete. When the not ACK is
latched by the slave, the slave logic is reset and the
slave then monitors for another occurrence of the
START bit. If the SDA line was low (ACK), the transmit
data must be loaded into the SSPBUF register, which
also loads the SSPSR register. Then, the SCL pin
should be enabled by setting the CKP bit.
FIGURE 15-12: I²C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
SDA
Receiving Address
R/W = 0
ACK
Receiving Data
ACK
Receiving Data
Not
ACK
A7 A6 A5 A4 A3 A2 A1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
SCL S ^{1 2 3 4} 5 ^{6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9}
P
SSPIF
BF (SSPSTAT<0>)
SSPOV (SSPCON1<6>)
Cleared in software
SSPBUF register is read
Bit SSPOV is set because the SSPBUF register is still full.
ACK is not sent.
Bus Master
Terminates
Transfer
FIGURE 15-13: I²C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
SDA
R/W = 1
Receiving Address
ACK
A7 A6 A5 A4 A3 A2 A1
R/W = 0
Transmitting Data Not ACK
D7 D6 D5 D4 D3 D2 D1 D0
SCL
S
1 23456789
1 2 34 56 789
Data in
SCL held low
P
sampled
while CPU
responds to SSPIF
SSPIF
BF (SSPSTAT<0>)
Cleared in software
From SSP Interrupt
SSPBUF is written in software Service Routine
CKP (SSPCON1<4>)
Set bit after writing to SSPBUF
(the SSPBUF must be written to
before the CKP bit can be set)
DS30289C-page 146
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