PIC17C7XX_13 Datasheet, PDF (200/306 Pages) Microchip Technology – High-Performance 8-bit CMOS EPROM Microcontrollers with 10-bit A/D

PIC17C7XX
TABLE 18-2: PIC17CXXX INSTRUCTION SET
Mnemonic,
Operands
Description
Cycles
16-bit Opcode
MSb
LSb
Status
Affected
Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF f,d
ADD WREG to f
1 0000 111d ffff ffff OV,C,DC,Z
ADDWFC f,d
ADD WREG and Carry bit to f
1 0001 000d ffff ffff OV,C,DC,Z
ANDWF f,d
AND WREG with f
1 0000 101d ffff ffff
Z
CLRF
f,s
Clear f, or Clear f and Clear WREG
1 0010 100s ffff ffff
None
3
COMF f,d
Complement f
1 0001 001d ffff ffff
Z
CPFSEQ f
Compare f with WREG, skip if f = WREG
1 (2) 0011 0001 ffff ffff
None
6,8
CPFSGT f
Compare f with WREG, skip if f > WREG
1 (2) 0011 0010 ffff ffff
None
2,6,8
CPFSLT f
Compare f with WREG, skip if f < WREG
1 (2) 0011 0000 ffff ffff
None
2,6,8
DAW
f,s
Decimal Adjust WREG Register
1 0010 111s ffff ffff
C
3
DECF
f,d
Decrement f
1 0000 011d ffff ffff OV,C,DC,Z
DECFSZ f,d
Decrement f, skip if 0
1 (2) 0001 011d ffff ffff
None
6,8
DCFSNZ f,d
Decrement f, skip if not 0
1 (2) 0010 011d ffff ffff
None
6,8
INCF
f,d
Increment f
1 0001 010d ffff ffff OV,C,DC,Z
INCFSZ f,d
Increment f, skip if 0
1 (2) 0001 111d ffff ffff
None
6,8
INFSNZ f,d
Increment f, skip if not 0
1 (2) 0010 010d ffff ffff
None
6,8
IORWF f,d
Inclusive OR WREG with f
1 0000 100d ffff ffff
Z
MOVFP f,p
Move f to p
1 011p pppp ffff ffff
None
MOVPF p,f
Move p to f
1 010p pppp ffff ffff
Z
MOVWF f
Move WREG to f
1 0000 0001 ffff ffff
None
MULWF f
Multiply WREG with f
1 0011 0100 ffff ffff
None
NEGW f,s
Negate WREG
1 0010 110s ffff ffff OV,C,DC,Z 1,3
NOP
—
No Operation
1 0000 0000 0000 0000
None
RLCF
f,d
Rotate left f through Carry
1 0001 101d ffff ffff
C
RLNCF f,d
Rotate left f (no carry)
1 0010 001d ffff ffff
None
RRCF
f,d
Rotate right f through Carry
1 0001 100d ffff ffff
C
RRNCF f,d
Rotate right f (no carry)
1 0010 000d ffff ffff
None
SETF
f,s
Set f
1 0010 101s ffff ffff
None
3
SUBWF f,d
Subtract WREG from f
1 0000 010d ffff ffff OV,C,DC,Z
1
SUBWFB f,d
Subtract WREG from f with Borrow
1 0000 001d ffff ffff OV,C,DC,Z
1
SWAPF f,d
Swap f
1 0001 110d ffff ffff
None
TABLRD t,i,f Table Read
2 (3) 1010 10ti ffff ffff
None
7
TABLWT t,i,f Table Write
2 1010 11ti ffff ffff
None
5
TLRD
t,f
Table Latch Read
1 1010 00tx ffff ffff
None
TLWT
t,f Table Latch Write
1 1010 01tx ffff ffff
None
Legend: Refer to Table 18-1 for opcode field descriptions.
Note 1: 2’s Complement method.
2: Unsigned arithmetic.
3: If s = '1', only the file is affected: If s = '0', both the WREG register and the file are affected; If only the Working register
(WREG) is required to be affected, then f = WREG must be specified.
4: During an LCALL, the contents of PCLATH are loaded into the MSB of the PC and kkkk kkkk is loaded into the LSB of the
PC (PCL).
5: Multiple cycle instruction for EPROM programming when table pointer selects internal EPROM. The instruction is termi-
nated by an interrupt event. When writing to external program memory, it is a two-cycle instruction.
6: Two-cycle instruction when condition is true, else single cycle instruction.
7: Two-cycle instruction except for TABLRD to PCL (program counter low byte), in which case it takes 3 cycles.
8: A “skip” means that instruction fetched during execution of current instruction is not executed, instead a NOP is executed.
DS30289C-page 200
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