TC1163 Datasheet, PDF (83/134 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller TriCore

TC1163/TC1164
Preliminary
Functional Description
OCDS Level 1 Debug Support
The OCDS Level 1 debug support is mainly assigned for real-time software debugging
purposes which have a demand for low-cost standard debugger hardware.
The OCDS Level 1 is based on a JTAG interface that is used by the external debug
hardware to communicate with the system. The on-chip Cerberus module controls the
interactions between the JTAG interface and the on-chip modules. The external debug
hardware may become master of the internal buses, and read or write the on-chip
register/memory resources. The Cerberus also makes it possible to define breakpoint
and trigger conditions as well as to control user program execution (run/stop, break,
single-step).
OCDS Level 2 Debug Support
The OCDS Level 2 debug support makes it possible to implement program tracing
capabilities for enhanced debuggers by extending the OCDS Level 1 debug functionality
with an additional 16-bit wide trace output port with trace clock. With the trace extension,
the following four trace capabilities are provided (only one of the four trace capabilities
can be selected at a time):
• Trace of the CPU program flow
• Trace of the PCP2 program flow
• Trace of the DMA Controller transaction requests
• Trace of the DMA Controller Move Engine status information
Data Sheet
79
V1.0, 2008-04