TC1163 Datasheet, PDF (33/134 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller TriCore

TC1163/TC1164
Preliminary
Functional Description
3.3.2 How to Read the Address Maps
The bus-specific address maps describe how the different bus master devices react on
accesses to on-chip memories and modules, and which address ranges are valid or
invalid for the corresponding buses.
The FPI Bus address map shows the system addresses from the point of view of the
SPB master agents. SPB master agents are PCP2 and OCDS, and DMA.
The LMB address map shows the system addresses from the point of view of the LMB
master agents. LMB master agents are PMI and DMI.
Table 3-2 defines the acronyms and other terms that are used in the address maps
(Table 3-3 to Table 3-5).
Table 3-2
Term
…BE
…BET
SPBBE
SPBBET
LMBBE
LMBBET
access
ignore
trap
32
nE
Definition of Acronyms and Terms
Description
Means “Bus error” generation.
Means “Bus error & trap” generation.
A bus access is terminated with a bus error on the SPB.
A bus access is terminated with a bus error on the SPB and a DSE
trap (read access) or DAE trap (write access).
A bus access is terminated with a bus error on the LMB.
A bus access is terminated with a bus error on the LMB and a DSE
trap (read access) or DAE trap (write access).
A bus access is allowed and is executed.
A bus access is ignored and is not executed. No bus error is
generated.
A DSE trap (read access) or DAE trap (write access) is generated.
Only 32-bit word bus accesses are permitted to that
register/address range.
A bus access generates no bus error, although the bus access
points to an undefined address or address range. This is valid e.g.
for CPU accesses (MTCR/MFCR) to undefined addresses in the
CSFR range.
Data Sheet
29
V1.0, 2008-04