TC1163 Datasheet, PDF (119/134 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller TriCore

TC1163/TC1164
Preliminary
Electrical Parameters
4.3.5 Phase Locked Loop (PLL)
Section 4.3.5 provides the characteristics of the PLL parameters and its operation in the
TC1163/TC1164.
Note: All PLL characteristics defined on this and the next page are verified by design
characterization.
Table 4-13 PLL Parameters (Operating Conditions apply)
Parameter
Symbol
Limit Values Unit
Min.
Max.
Accumulated jitter
VCO frequency range
D_P
See Figure 4-12
–
f_VCO
400
500
MHz
500
600
MHz
PLL base frequency¹⁾
600
700
MHz
f_PLLBASE 140
320
MHz
150
400
MHz
200
480
MHz
PLL lock-in time
t_L
–
200
µs
1) The CPU base frequency which is selected after reset is calculated by dividing the limit values by 16 (this is
the K factor after reset).
Phase Locked Loop Operation
When PLL operation is enabled and configured, the PLL clock f_VCO (and with it the CPU
clock f_CPU) is constantly adjusted to the selected frequency. The relation between f_VCO
and f_SYS is defined by: f_VCO = K × f_CPU. The PLL causes a jitter of f_CPU and affects the
clock outputs TRCLK and SYSCLK (P4.3) which are derived from the PLL clock f_VCO.
There are two formulas that define the (absolute) approximate maximum value of jitter
D_P in ns dependent on the K-factor, the CPU clock frequency f_CPU in MHz, and the
number P of consecutive f_CPU clock periods.
P × K < 900
Dp[ns] = ±_{f---c---p---5u----[}-^×-M---P---H----z---_]- + 0, 9_
(4.1)
P × K ≥ 900
Dp[ns]
=
±
---------------4---5---0---0----------------
fcpu[MHz] × K
+ 0, 9_
(4.2)
K : K-Divider Value
P : Number of f_CPU periods
D_P : Jitter in ns
f_CPU : CPU frequency in MHz
Data Sheet
115
V1.0, 2008-04