TC1163 Datasheet, PDF (31/134 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller TriCore

TC1163/TC1164
Preliminary
Functional Description
3.3
Memory Maps
This chapter gives an overview of the TC1163/TC1164 memory map and describes the
address locations and access possibilities for the units, memories, and reserved areas
as “seen” from different on-chip buses’ (SPB and LMB) point of view.
3.3.1 Architectural Address Map
Table 3-1 shows the overall architectural address map as defined for the TriCore and as
implemented in TC1163/TC1164.
Table 3-1 TC1163/TC1164 Architectural Address Map
Seg- Contents
ment
Size
Description
0-7 Global
8 x 256
Mbyte
Reserved (MMU space); cached
8
Global
256 Mbyte Reserved (246 Mbyte); PMU, Boot ROM;
Memory
cached
9
Global
256 Mbyte FPI space; cached
Memory
10
Global
Memory
256 Mbyte Reserved (246 Mbyte), PMU, Boot ROM; non-
cached
11
Global
Memory
256 Mbyte FPI space; non-cached
12
Local LMB 256 Mbyte Reserved; bottom 4 Mbyte visible from FPI bus
Memory
in segment 14; cached
13
DMI
64 Mbyte Local Data Memory RAM; non-cached
PMI
64 Mbyte Local Code Memory RAM; non-cached
EXT_PER 96 Mbyte Reserved; non-cached
EXT_EMU 16 Mbyte Reserved; non-cached
BOOTROM
16 Mbyte
Boot ROM space, Boot ROM mirror;
non-cached
Data Sheet
27
V1.0, 2008-04