TC1163 Datasheet, PDF (53/134 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller TriCore

TC1163/TC1164
Preliminary
Functional Description
3.6
DMA Controller and Memory Checker
The DMA Controller of the TC1163/TC1164 transfers data from data source locations to
data destination locations without intervention of the CPU or other on-chip devices. One
data move operation is controlled by one DMA channel. Eight DMA channels are
provided in one DMA Sub-Block. The Bus Switch provides the connection of the DMA
Sub-Block to the two FPI Bus interfaces and an MLI bus interface. In the
TC1163/TC1164, the FPI Bus interfaces are connected to the System Peripheral Bus
and the DMA Bus. The third specific bus interface provides a connection to Micro Link
Interface modules (two MLI modules in the TC1163/TC1164) and other DMA-related
devices (Memory Checker module in the TC1163/TC1164). Clock control, address
decoding, DMA request wiring, and DMA interrupt service request control are
implementation-specific and managed outside the DMA controller kernel. Figure 3-2
shows the implementation details and interconnections of the DMA module.
Clo ck
Co n tr o l
f _DMA
DMA Controller
DMA
Re q u e sts
of
On-chip
Periph.
Un its
DMA Sub-Block 0
Re q u e st
CSHe0lne_ctOioUnT/
A rb itr a tio n
DMA
Channels
00-07
Tr a n sa ctio n
Control Unit
Bus
S witch
A d d re ss
Decoder
Interrupt _SR[15:0]
Request
Nodes
DMA Interrupt Control
A r b ite r /
S witch
Co n tr o l
S yste m
Periphera
Bus
DMA Bus
M L I0
Memory
Ch e cke r
Figure 3-2 DMA Controller Block Diagram
TC1163/TC1164 DMA Block Diagram
Data Sheet
49
V1.0, 2008-04