TC1163 Datasheet, PDF (66/134 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller TriCore

TC1163/TC1164
Preliminary
Functional Description
Figure 3-9 shows a global view of the functional blocks of the MLI module with its
interfaces.
Clock
f_{ML I0}
Control
Address
Decoder
Interrupt
Control
SR[3:0]
MLI 0
Module
(Kernel )
SR[4:7]
To DMA
BRKOUT
Cerberus
TCLK
TREADYA
TREADYB
TREADYD
TVALIDA
TVALIDB
TVALIDD
TDATA
RCLKA
RCLKB
RCLKD
RREADYA
RREADYB
RREADYD
RVALIDA
RVALIDB
RVALIDD
RDATAA
RDATAB
RDATAD
Port 2
Control
A2 P2.0 / TCLK0
A2 P2.1 / TREADY0A
A2 P2.2 / TVALID0A
A2 P2.3 / TDATA0
A1 P2.4 / RCLK0A
A2 P2.5 / RREADY0A
A1 P2.6 / RVALID0A
A1 P2.7 / RDATA0A
Port 5
Control
A2 P5.15 / TCLK0
A2 P5.14 / TREADY0B
A2 P5.13 / TVALID0B
A2 P5.12 / TDATA0
A2 P5.11 / RCLK0B
A2 P5.10 / RREADY0B
A2 P5.9 / RVALID0B
A2 P5.8 / RDATA0B
TC 1163/TC1164 MLI Block Diagram
Figure 3-9 Block Diagram of the MLI Module
Data Sheet
62
V1.0, 2008-04