TC1163 Datasheet, PDF (76/134 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller TriCore

TC1163/TC1164
Preliminary
Functional Description
The STM can also be read in sections from seven registers, STM_TIM0 through
STM_TIM6, that select increasingly higher-order 32-bit ranges of the STM. These can
be viewed as individual 32-bit timers, each with a different resolution and timing range.
The content of the 56-bit System Timer can be compared with the content of two
compare values stored in the STM_CMP0 and STM_CMP1 registers. Interrupts can be
generated on a compare match of the STM with the STM_CMP0 or STM_CMP1
registers.
The maximum clock period is 2⁵⁶ × f_STM. At f_STM = 80 MHz, for example, the STM counts
28.56 years before overflowing. Thus, it is capable of timing the entire expected product
life-time of a system without overflowing continuously.
Figure 3-13 shows an overview on the System Timer with the options for reading parts
of the STM contents.
Data Sheet
72
V1.0, 2008-04