TC1163 Datasheet, PDF (71/134 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller TriCore

TC1163/TC1164
Preliminary
Functional Description
3.14
Analog-to-Digital Converter (ADC0)
Section 3.14 shows the global view of the ADC module with its functional blocks and
interfaces and the features which are provided by the module.
V_DD
V_DDM
V_AGND0 V_SS V_SSM V_AREF0
f_ADC
Clock
Control ^fCLC
Address
Decoder
GPRS
EMUX0
EMUX1
Port 1
Control
ASGT
SW0TR, SW0GT
ETR, EGT
QTR, QGT
TTR, TGT
External
Request
Unit
(SCU)
A1
P1.14 /
AD0EMUX2 (GRPS)
A1 ^{P1.13 /AD0EMUX1}
A1 P1.12 /AD0EMUX0
8 _{From Ports}
2 _{From MSC0}
6 _{From GPTA}
Interrupt ^SR[3:0]
Control
SR[7:4]
To DMA
ADC0
Module
Kernel
Group 0
AIN0
AIN15
Group 1
AIN16
AIN30
AIN31
0
Die
1
Temperature
Measurement
D AN0
D AN15
D AN16
D AN30
D AN31
SCU_CON.DTSON
MCA06427
Figure 3-11 Block Diagram of the ADC Module
The ADC module has 16 analog input channels. An analog multiplexer selects the input
line for the analog input channels from among 32 analog inputs. Additionally, an external
analog multiplexer can be used for analog input extension. External Clock control,
address decoding, and service request (interrupt) control are managed outside the ADC
module kernel. External trigger conditions are controlled by an External Request Unit.
This unit generates the control signals for auto-scan control (ASGT), software trigger
control (SW0TR, SW0GT), the event trigger control (ETR, EGT), queue control (QTR,
QGT), and timer trigger control (TTR, TGT).
An automatic self-calibration adjusts the ADC module to changing temperatures or
process variations. Figure 3-11 shows the global view of the ADC module with its
functional blocks and interfaces.
Data Sheet
67
V1.0, 2008-04