TC1163 Datasheet, PDF (129/134 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller TriCore

TC1163/TC1164
Preliminary
Electrical Parameters
4.3.8.3 Synchronous Serial Channel (SSC) Master Mode Timing
Table 4-19 provides the characteristics of the SSC timing in the TC1163/TC1164.
Table 4-19 SSC Master Mode Timing (Operating Conditions apply, C_L = 50 pF)
Parameter
Symbol
Limit Values
Unit
Min.
Max.
SCLK clock period¹⁾²⁾
t₅₀
CC 2 × T_SSC3) –
ns
MTSR/SLSOx delay from SCLK
t₅₁
CC 0
8
ns
MRST setup to SCLK
t₅₂
SR 10
–
ns
MRST hold from SCLK
t₅₃
SR 5
–
ns
1) SCLK signal rise/fall times are the same as the A2 Pads rise/fall times.
2) SCLK signal high and low times can be minimum 1 × T_SSC.
3) T_SSCmin = T_SYS = 1/f_SYS. When f_SYS = 80 MHz, t₅₀ = 25ns
t₅₀
SCLK¹⁾²⁾
t₅₁
t₅₁
MTSR¹⁾
MRST¹⁾
SLSOx²⁾
t₅₂
t₅₃
Data
valid
t₅₁
1) This timing is based on the following setup: CON.PH = CON.PO = 0.
2) The transition at SLSOx is based on the following setup: SSOTC.TRAIL = 0
and the first SCLK high pulse is in the first one of a transmission.
SSC_Tmg_1.vsd
Figure 4-19 SSC Master Mode Timing
Data Sheet
125
V1.0, 2008-04