TC1163 Datasheet, PDF (34/134 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller TriCore

TC1163/TC1164
Preliminary
3.3.3 Contents of the Segments
This section summarizes the contents of the segments.
Functional Description
Segments 0-7
These segments are reserved segments in the TC1163/TC1164.
Segment 8
From the SPB point of view (PCP, DMA and Cerberus), this memory segment allows
accesses to all PMU memories (PFLASH, DFLASH, BROM, and TROM).
From the CPU point of view (PMI and DMI), this memory segment allows cached
accesses to all PMU memories (PFLASH, DFLASH, BROM, and TROM).
Segment 9
This memory segment is reserved in the TC1163/TC1164.
Segment 10
From the SPB point of view (PCP, DMA and Cerberus), this memory segment allows
accesses to all PMU memories (PFLASH, DFLASH, BROM, and TROM).
From the CPU point of view (PMI and DMI), this memory segment allows non-cached
accesses to all PMU memories (PFLASH, DFLASH, BROM, and TROM).
Segment 11
This memory segment is reserved in the TC1163/TC1164.
Segment 12
From the SPB point of view (PCP, DMA, and Cerberus), this memory segment is
reserved in the TC1163/TC1164.
From the CPU point of view (PMI and DMI), this memory segment allows cached
accesses to the PMU memory, OVRAM.
Segment 13
From the SPB point of view (PCP, DMA and Cerberus), this memory segment is
reserved in the TC1163/TC1164.
From the CPU point of view (PMI and DMI), this memory segment allows non-cached
accesses to the PMI scratch-pad RAM, read access to the boot ROM and test ROM
(BROM and TROM) and the DMI memories (LDRAM).
Data Sheet
30
V1.0, 2008-04