TC1163 Datasheet, PDF (55/134 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller TriCore

TC1163/TC1164
Preliminary
Functional Description
Note: Although the polynomial above is used for generation, the generation algorithm
differs from the one that is used by the Ethernet protocol.
3.7
Interrupt System
The TC1163/TC1164 interrupt system provides a flexible and time-efficient means of
processing interrupts. An interrupt request can be serviced either by the CPU or by the
Peripheral Control Processor (PCP). These units are called “Service Providers”.
Interrupt requests are called “Service Requests” rather than “Interrupt Requests” in this
document because they can be serviced by either Service Providers.
Each peripheral in the TC1163/TC1164 can generate service requests. Additionally, the
Bus Control Units, the Debug Unit, the PCP, and even the CPU itself can generate
service requests to either of the two Service Providers.
As shown in Figure 3-3, each TC1163/TC1164 unit that can generate service requests
is connected to one or multiple Service Request Nodes (SRN). Each SRN contains a
Service Request Control Register mod_SRCx, where “mod” is the identifier of the
service requesting unit and “x” an optional index. Two arbitration buses connect the
SRNs with two Interrupt Control Units, which handle interrupt arbitration among
competing interrupt service requests, as follows:
• The Interrupt Control Unit (ICU) arbitrates service requests for the CPU and
administers the CPU Interrupt Arbitration Bus.
• The Peripheral Interrupt Control Unit (PICU) arbitrates service requests for the PCP
and administers the PCP Interrupt Arbitration Bus.
The PCP can make service requests directly to itself (via the PICU), or it can make
service requests to the CPU. The Debug Unit can generate service requests to the PCP
or the CPU. The CPU can make service requests directly to itself (via the ICU), or it can
make service requests to the PCP. The CPU Service Request Nodes are activated
through software.
Depending on the selected system clock frequency f_SYS, the number of f_SYS clock cycles
per arbitration cycle must be selected as follows:
• f_SYS < 60 MHz: ICR.CONECYC = 1 and PCP_ICR.CONECYC = 1
• f_SYS > 60 MHz: ICR.CONECYC = 0 and PCP_ICR.CONECYC = 0
Data Sheet
51
V1.0, 2008-04