TC1163 Datasheet, PDF (50/134 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller TriCore

TC1163/TC1164
Preliminary
Functional Description
3.4
Memory Protection System
The TC1163/TC1164 memory protection system specifies the addressable range and
read/write permissions of memory segments available to the current executing task. The
memory protection system controls the position and range of addressable segments in
memory. It also controls the types of read and write operations allowed within
addressable memory segments. Any illegal memory access is detected by the memory
protection hardware, which then invokes the appropriate Trap Service Routine (TSR) to
handle the error. Thus, the memory protection system protects critical system functions
against both software and hardware errors. The memory protection hardware can also
generate signals to the Debug Unit to facilitate tracing illegal memory accesses.
There are two Memory Protection Register Sets in the TC1163/TC1164, numbered 0
and 1, which specify memory protection ranges and permissions for code and data. The
PSW.PRS bit field determines which of these is the set currently in use by the CPU. As
the TC1163/TC1164 uses a Harvard-style memory architecture, each Memory
Protection Register Set is broken down into a Data Protection Register Set and a Code
Protection Register Set. Each Data Protection Register Set can specify up to four
address ranges to receive a particular protection modes. Each Code Protection Register
Set can specify up to two address ranges to receive a particular protection modes.
Each Data Protection Register Sets and Code Protection Register Sets determines the
range and protection modes for a separate memory area. Each set contains a pair of
registers which determine the address range (the Data Segment Protection Registers
and Code Segment Protection Registers) and one register (Data Protection Mode
Register) which determines the memory access modes that applies to the specified
range.
3.5
Peripheral Control Processor
The Peripheral Control Processor (PCP2) in the TC1163/TC1164 performs tasks that
would normally be performed by the combination of a DMA controller and its supporting
CPU interrupt service routines in a traditional computer system. It could easily be
considered as the host processor’s first line of defence as an interrupt-handling engine.
The PCP can unload the CPU from having to service time-critical interrupts. This
provides many benefits, including:
• Avoiding large interrupt-driven task context-switching latencies in the host processor
• Reducing the cost of interrupts in terms of processor register and memory overhead
• Improving the responsiveness of interrupt service routines to data-capture and data-
transfer operations
• Easing the implementation of multitasking operating systems
The PCP2 has an architecture that efficiently supports DMA-type transactions to and
from arbitrary devices and memory addresses within the TC1163/TC1164 and also has
reasonable stand-alone computational capabilities.
Data Sheet
46
V1.0, 2008-04