TC1163 Datasheet, PDF (75/134 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller TriCore

TC1163/TC1164
Preliminary
Functional Description
3.16
System Timer
The TC1163/TC1164’s STM is designed for global system timing applications requiring
both high precision and long period.
Features
• Free-running 56-bit counter
• All 56 bits can be read synchronously
• Different 32-bit portions of the 56-bit counter can be read synchronously
• Flexible interrupt generation based on compare match with partial STM content
• Driven by maximum 80 MHz (= f_SYS, default after reset = f_SYS/2)
• Counting starts automatically after a reset operation
• STM is reset by:
– Watchdog reset
– Software reset (RST_REQ.RRSTM must be set)
– Power-on reset
• STM (and clock divider STM_CLC.RMC) is not reset at a hardware reset (HDRST =
0)
• STM can be halted in debug/suspend mode (via STM_CLC register)
The STM is an upward counter, running either at the system clock frequency f_SYS or at a
fraction of it. The STM clock frequency is f_STM = f_SYS/RMC with RMC = 0-7 (default after
reset is f_STM = f_SYS/2, selected by RMC = 010_B). RMC is a bit field in register STM_CLC.
In case of a power-on reset, a watchdog reset, or a software reset, the STM is reset. After
one of these reset conditions, the STM is enabled and immediately starts counting up. It
is not possible to affect the content of the timer during normal operation of the
TC1163/TC1164. The timer registers can only be read but not written to.
The STM can be optionally disabled for power-saving purposes, or suspended for
debugging purposes via its clock control register. In suspend mode of the
TC1163/TC1164 (initiated by writing an appropriate value to STM_CLC register), the
STM clock is stopped but all registers are still readable.
Due to the 56-bit width of the STM, it is not possible to read its entire content with one
instruction. It needs to be read with two load instructions. Since the timer would continue
to count between the two load operations, there is a chance that the two values read are
not consistent (due to possible overflow from the low part of the timer to the high part
between the two read operations). To enable a synchronous and consistent reading
operation of the STM content, a capture register (STM_CAP) is implemented. It latches
the content of the high part of the STM each time when one of the registers STM_TIM0
to STM_TIM5 is read. Thus, STM_CAP holds the upper value of the timer at exactly the
same time when the lower part is read. The second read operation would then read the
content of the STM_CAP to get the complete timer value.
Data Sheet
71
V1.0, 2008-04