TC1163 Datasheet, PDF (120/134 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller TriCore

TC1163/TC1164
Preliminary
Electrical Parameters
Note: The frequency of system clock f_SYS can be selected to be either f_CPU or f_CPU/2.
With rising number P of clock cycles the maximum jitter increases linearly up to a value
of P that is defined by the K-factor of the PLL. Beyond this value of P the maximum
accumulated jitter remains at a constant value. Further, a lower CPU clock frequency
f_CPU results in a higher absolute maximum jitter value.
Figure 4-12 illustrates the jitter curve for several K/ f_CPU combinations.
±13.0
TC1163/TC1164 PLL Jitter (Preliminary)
±12.0
±11.0
f_CPU = 40 MHz (K = 10)
f_CPU = 80 MHz (K = 5)
±10.0
±9.0
±8.0
f_CPU = 40 MHz
(K = 17)
f_CPU = 66 MHz ( K = 7)
f_CPU = 80 MHz (K = 8)
±7.0
f_CPU = 66 MHz (K = 10)
±6.0
±5.0
±4.0
±3.0
±2.0
±1.0
±0.0
1
25
50
75
100
125
150
175
oo
P [Periods]
TC1163/TC1164 PLL Jitter
Figure 4-12 Approximated Maximum Accumulated PLL Jitter for Typical CPU
Clock Frequencies f_CPU (overview)
Data Sheet
116
V1.0, 2008-04