TC1163 Datasheet, PDF (115/134 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller TriCore

TC1163/TC1164
Preliminary
Electrical Parameters
4.3.3 Power Sequencing
There is a restriction for the power sequencing of the 3.3 V domain as shown in
Figure 4-9. It must always be higher than 1.5 V domain - 0.5 V. The gray area shows the
valid range for V_3.3V relative to an exemplary V_1.5V ramp. V_DDP, V_DDOSC3, V_DDM, V_DDMF,
V_DDFL3 belong to the 3.3 V domain. The V_DDM and V_DDMF subdomains are connected with
antiparallel ESD protection diodes. There are no other such connections between the
subdomains. V_{DD ,} V_DDOSC and V_DDAF belong to the 1.5 V domain.
Power Supply Voltage
3.3V
1.5V
V_{D D P}
(3.3V)
PORST
V_3.3 > V_1.5 - 0.5V
V_{3 . 3}
V
1.5
Time
Time
PowerSeq
Figure 4-9 Power Up Sequence
All ground pins V_SS must be externally connected to one single star point in the system.
The difference voltage between the ground pins must not exceed 200 mV.
The PORST signal must be activated at latest before any power supply voltage falls
below the levels shown on the figure below. In this case, only the memory row of a Flash
memory that was the target of the write at the moment of the power loss will contain
unreliable content. Additionally, the PORST signal should be activated as soon as
possible. The sooner the PORST signal is activated, the less time the system operates
outside of the normal operating power supply range.
Data Sheet
111
V1.0, 2008-04