33742_08 Datasheet, PDF (69/70 Pages) Freescale Semiconductor, Inc – System Basis Chip with Enhanced High Speed CAN Transceiver

REVISION DATE
3
2/2006
4
6/2006
5
8/2006
6
8/2006
7
10/2006
8
2/2007
9
3/2007
10
5/2007
11
6/2008
REVISION HISTORY
REVISION HISTORY
DESCRIPTION OF CHANGES
• Converted to Freescale format
• Implemented Revision History page
• Added Thermal Addendum (Rev. 1.0)
• Changed Data Sheet from “Advanced” to “Final”
• Added MCZ33742EG/R2 and MCZ33742SEG/R2 to the Ordering Information block
• Replaced label for Logic Inputs to Logic Signals (RXD, TXD, MOSI, MISO, CS, SCLK, RST,
WDOG, and INT) on page 7
• Removed all references to the 54 pin package.
• Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from
Maximum Ratings on page 7. Added note with instructions from www.freescale.com.
• Revised () and (),
• Restated notes in Maximum Ratings on page 7
• Text corrections to the included thermal addendum
• Added EP 48 pin QFN package
• Added 98ARH99048A Package drawing
• Added PCZ33742EP/R2 to the ordering information
• Made changes defining RXD as a push-pull structure on page 16, 23, 38, and 39
• Updated figures Figure 12 and Figure 25
• Added provisions of differentiation for 28-pin SOIC and 48-pin QFN for ESD Capability,
Human Body Model⁽¹⁾ on page 7, Watchdog Period Normal and Standby Modes on page 18,
and Normal Request Mode Timeout on page 18
• Update the Freescale format and style to the current standards
• Added the Functional Internal Block Description section
• Changed PCZ33742EP/R2 to MC33742EP/R2 in the ordering information
Analog Integrated Circuit Device Data
Freescale Semiconductor
33742
69