33742_08 Datasheet, PDF (50/70 Pages) Freescale Semiconductor, Inc – System Basis Chip with Enhanced High Speed CAN Transceiver

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
HIGH-SPEED CAN TRANSCEIVER MODES
The MODE bit (D0) controls the state of the CAN interface, TXRX or Sleep mode (Table 22). SC0 bit (D1) defines the slew
rate when the CAN module is in TXRX, and it controls the wake-up option (wake-up enable or disable) when the CAN module is
in Sleep mode.
Table 22. CAN High-Speed Transceiver Modes
SC1
SC0
MODE
CAN Mode
(Pass 1.1)
0
0
0
0
1
0
1
0
0
1
1
0
x
1
1
x
0
1
CAN TXRX, Slew Rate 0
CAN TXRX, Slew Rate 1
CAN TXRX, Slew Rate 2
CAN TXRX, Slew Rate 3
CAN Sleep and CAN Wake-up Disable
CAN Sleep and CAN Wake-up Enable
x = Don’t care.
Table 23. CAN Register Status Bits
Name
Logic
Description
0
CANWU
1
0
CAN-F
1
0
CAN-UF
1
0
THERM-CUR
1
Notes
58. Error bits are latched in the CAN register.
No CAN wake-up occurred.
CAN wake-up occurred.
No CAN failure.
CAN failure⁽⁵⁸⁾.
Identified CAN failure⁽⁵⁸⁾.
Non-identified CAN failure.
No over-temperature or over-current on CANH or CANL drivers.
Over-temperature or over-current on CANH or CANL drivers.
INPUT / OUTPUT REGISTER (IOR)
Tables 24 through 26 contain the Input / Output Register information. Table 25 provides information about information HS control
in Normal and Standby modes, while Table 26 provides status bit information.
Table 24. Input / Output Register
IOR
R/W
D3
D2
D1
D0
$011b
W
–
R
V2LOW
Reset Value
–
–
Reset Condition
–
–
(Write)⁽⁵⁹⁾
Notes
59. See Table 13, page 47, for definitions of reset conditions.
HSON
HSOT
0
POR
–
VSUPLOW
–
–
–
DEBUG
–
–
33742
50
Analog Integrated Circuit Device Data
Freescale Semiconductor