33742_08 Datasheet, PDF (53/70 Pages) Freescale Semiconductor, Inc – System Basis Chip with Enhanced High Speed CAN Transceiver

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 31. TIM1 Control Bits
WDW
WDT1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
WDT0
0
1
0
1
0
1
0
1
Timing (ms typ)
9.75
45
100
350
9.75
45
100
350
Window Closed
No Watchdog Clear Allowed Window Open for Watchdog Clear
Parameter
Watchdog Period 1
Watchdog Period 2
Watchdog Period 3
Watchdog Period 4
Watchdog Period 1
Watchdog Period 2
Watchdog Period 3
Watchdog Period 4
Description
No Window Watchdog
Watchdog Window enabled
(Window length is half the
Watchdog Timing).
Window Open for Watchdog Clear
Watchdog Timing x 50%
Watchdog Timing x 50%
Watchdog Period
(Watchdog Timing Selected by TIM1 Bit WDW =1)
Figure 28. Window Watchdog
Watchdog Period
(Watchdog Timing Selected by TIM1 Bit WDW = 0)
Figure 29. Timeout Watchdog
Table 32. Timing Register Status Bits
Name
CANL2VDD
CANL2BAT
CANL2GND
TXPD
Logic
0
1
0
1
0
1
0
1
Failure Description
No CANL short to VDD.
CANL short to VDD.
No CANL short to VSUP .
CANL short to VSUP .
No CANL short to GND.
CANL short to GND.
No TXD dominant.
TXD dominant.
Table 33. TIM2 Timing and CANL Failure Diagnostic Register
TIM2
R/W
D3
D2
$101b
W
1
R
CANL2VDD
Reset Value
–
–
Reset Condition (Write)⁽⁶⁴⁾
–
–
Notes
64. See Table 13, page 47, for definitions of reset conditions.
CSP2
CANL2BAT
0
POR, RESET
D1
CSP1
CANL2GND
0
POR, RESET
D0
CSP0
TXPD
0
POR, RESET
Analog Integrated Circuit Device Data
Freescale Semiconductor
33742
53