33742_08 Datasheet, PDF (30/70 Pages) Freescale Semiconductor, Inc – System Basis Chip with Enhanced High Speed CAN Transceiver

FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
mode over-current situation or from forced wake-up, no bits
are set. After the INT pulse, the 33742 accepts SPI command
after a time delay (t _S-1STSPI).
WATCHDOG SOFTWARE IN STOP MODE
If the SBC watchdog is enabled, the application must
provide a “system ok” response before the end of the 33742
watchdog time. Typically an MCU initiates the wake-up of the
33742 through the SPI wake-up (CS activation). The SBC will
awaken and jump into the Normal Request mode. The MCU
has to configure the 33742 to go to either Normal or Standby
mode. The MCU can then decide to return to the Stop mode.
If no MCU wake-up occurs within the watchdog time
period, the SBC activates the RST pin and jumps into the
Normal Request mode. The MCU can then be re-initialized.
SPI Stop/Sleep
Command
SPI CS
STOP MODE ENTER COMMAND
Stop mode is entered at the end of the SPI message at the
rising edge of the CS. (Refer to the t _CS-STOP data in the
Dynamic Electrical Characteristics table on page 17.) Once
Stop mode is entered, the SBC can wake up from a VDD
regulator over-current detection state. In order to allow time
for the MCU to complete the last CPU instruction and enter
its low power mode, a deglitcher time of 40μs typical is
implemented.
Figure 11, page 30, depicts the operation of entering the
Stop mode.
t _CS-STOP
33742 in Normal
or Standby mode
t _IDD-DGLT
33742 in Stop mode.
No I_DD over I_DD-DGLT
33742 in Stop mode.
I_DD over I_DD-DGLT
Figure 11. Entering the Stop Mode
WATCHDOG SOFTWARE (RST AND WDOG)
(SELECTABLE WATCHDOG WINDOW OR
WATCHDOG TIME-OUT)
A watchdog is used in the SBC Normal and Standby
modes for monitoring the MCU operation. The watchdog
timer may be implemented as either a watchdog window or
watchdog timeout, selectable by SPI (TIM1 sub register, bit
WDW). Default operation is a watchdog window.
The watchdog period can be set from 10ms to 350ms
(TIM1 sub register, bits WDT0 and WDT1). When a watchdog
window is selected, the closed window is the first part of the
selected period, and the open window is the second part of
the period. (Refer to Timing Register (TIM1 / 2) beginning on
page 52.)
The watchdog can only be cleared within the open window
time period. Any attempt to clear watchdog in the closed
window will generate a reset. The watchdog is cleared
addressing the TIM1 sub register using the SPI
RST PIN DESCRIPTION
A 33742 output is available to perform a reset of the MCU.
Reset can happen from:
• V_DD Falling Out of Range—If V_DD falls below the reset
threshold (V _RSTTH), the RST pin is pulled LOW until
V_DD returns to the normal voltage.
• Power-ON Reset—At 33742 power-on or wake-up from
Sleep mode, the RST pin is maintained LOW until V_DD
is within its operation range.
• Watchdog Timeout—If watchdog is not cleared, the
33742 will pull the RST pin LOW for the duration of the
reset time (t _RSTDUR).
RST AND WDOG OPERATION
Table 8 describes watchdog and reset output modes of
operation. RST is activated in the event V_DD fall or watchdog
is not triggered. WDOG output is active LOW as soon as RST
goes LOW and stays LOW as long as the watchdog is not
properly reset via SPI. The WDOG output pin is designed as
a push-pull structure that can drive off chip components
signaling, for instance, errant MCU operation.
Figure 12 illustrates the device behavior in the event the
TIM1 register in not properly accessed. In this case, a
software reset occurs and the WDOG pin is set LOW until the
TIM1 register is properly accessed.
33742
30
Analog Integrated Circuit Device Data
Freescale Semiconductor