33742_08 Datasheet, PDF (22/70 Pages) Freescale Semiconductor, Inc – System Basis Chip with Enhanced High Speed CAN Transceiver

ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
CS
SCLK
MOSI
MISO
t _LEAD
t _PCLK
t _WSCLKH
Undefined
t _VALID
t _SOEN
t _SISU
t _WSCLKL
t _SIH
DI 0
Don’t Care
DO 0
t _LAG
DI 8
Don’t Care
t _SODIS
DO 8
Note Incoming data at MOSI pin is sampled by the 33742 at SCLK falling edge. Outgoing data at MISO pin
is set by the 33742 at SCLK rising edge (after t_VALID delay time).
Figure 7. SPI Timing Diagram
TXD
t_LRD
0.8 V
2.0 V
t_LDR
RXD
0.8 V
2.0 V
Figure 8. Propagation Loop Delay TXD to RXD
TXD
t_TRD
0.8 V
2.0 V
t_TDR
V_DIFF
0.9 V
0.5 V
V_DIFF = V_CANH - V_CANL
Figure 9. Propagation Delay TXD to CAN
0.9 V
V_DIFF
t_RRD
0.5 V
t_RDR
RXD
0.8 V
2.0 V
Figure 10. Propagation Delay CAN to RXD
33742
22
Analog Integrated Circuit Device Data
Freescale Semiconductor