33742_08 Datasheet, PDF (55/70 Pages) Freescale Semiconductor, Inc – System Basis Chip with Enhanced High Speed CAN Transceiver

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 36. LX2HS Control Bits
Logic
Wake-up Inputs Supplied by HS
0
No.
1
Yes. Lx inputs sensed at sampling point.
Table 37. HSAUTO Control Bits
Logic
Auto-timing HS in Sleep and Stop modes
0
OFF.
1
ON, HS Cyclic, period defined in TIM2 subregister.
Table 38. CAN-INT Control Bits
Logic⁽⁶⁶⁾
Description
0
Interrupt as soon as CAN bus failure detected.
1
Interrupt when CAN bus failure detected and fully identified.
Notes
66. If CAN-INT is at logic [0], any undetermined CAN failure will be latched in the CAN register (bit D1: CAN-UF) and can be accessed by
SPI (refer to CAN Register (CAN) on page 49). After reading the CAN register or setting CAN-INT to logic [1], it will be cleared
automatically. The existence of CAN-UF always has priority over clearing, meaning that a further undetermined CAN failure does not
allow clearing the CAN-UF bit.
Table 39. LPC Status Bits
Name
CANH2VDD
CANH2BAT
CANH2GND
RXPR
Logic
0
1
0
1
0
1
0
1
Failure Description
No CANH short to V_DD.
CANH short to V_DD.
No CANH short to VSUP.
CANH short to VSUP.
No CANH short to GND.
CANH short to GND.
No RXD permanent recessive.
RXD permanent recessive.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33742
55