33742_08 Datasheet, PDF (59/70 Pages) Freescale Semiconductor, Inc – System Basis Chip with Enhanced High Speed CAN Transceiver

TYPICAL APPLICATIONS
VDD
Watchdog Refresh
Missing Watchdog Refresh
SPI (CS)
WD
RST
350ms
Watchdog
Refresh
INT
SBC in
Reset
mode
SBC in Normal Request
& Reset modes
Reset each 350ms
SBC in Normal
mode
SBC in Normal
Request & Reset
mode
Figure 33. Power up sequence, No W/D write at first
POWER UP AND VDD GOING LOW WITH STOP MODE AS DEFAULT LOW POWER MODE IS SELECTED
The first part of Figure 34 is identical to Figure 33. If VDD is pulled below VDD under-voltage reset (typ 4.6V), say by an over-
current or short-circuit (for instance, short to 4.0V), and if a low power mode previously selected was Stop mode, the 33742 enters
Reset mode (RST pin is active). The WDOG pin stays HIGH, but the high level (Voh) follows V1 level. The INT pin goes LOW.
When the VDD overload condition is removed, the 33742 restarts in Normal Request mode.
VDD
SPI (CS)
Watchdog Refresh
Under-voltage at VDD (VDD < V_RSTTH)
350ms
WD
RST
INT
SBC in
Reset
mode
SBC in Normal Request
& Reset modes
SBC in Normal
mode
SBC in Normal
Reset mode
Reset each 350ms
Figure 34. Under-voltage on VDD
Analog Integrated Circuit Device Data
Freescale Semiconductor
33742
59