33742_08 Datasheet, PDF (49/70 Pages) Freescale Semiconductor, Inc – System Basis Chip with Enhanced High Speed CAN Transceiver

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
RESET CONTROL REGISTER (RCR)
Tables 18 and 19 contain various Reset Control Register information.
Table 18. Reset Control Register
RCR
R/W
D3
D2
D1
$001b
W
WDSTOP
R
NOSTOP
Reset Value
–
1
0
Reset Condition
(Write)⁽⁵⁶⁾
–
POR, RESET, STO2NR POR, NR2N, NR2STB
Notes
56. See Table 13 page 47, for definitions of reset conditions.
CAN SLEEP
0
POR, NR2N, NR2STB
D0
RSTTH
0
POR
Table 19. Reset Control Register Control Bits
Name
Logic
Description
WDSTOP
NOSTOP
CAN SLEEP
RSTTH
0
No Watchdog in Stop mode.
1
Watchdog runs in Stop mode.
0
Device cannot enter Sleep mode.
1
Sleep mode allowed. Device can enter Sleep mode.
0
CAN Sleep mode disable (despite D0 bit in CAN register).
1
CAN Sleep mode enabled (in addition to D0 in CAN register).
0
Reset Threshold 1 selected (typ 4.6V).
1
Reset Threshold 2 selected (typ 4.2V).
CAN REGISTER (CAN)
Tables 20 through 23 contain the information on the CAN register. Table 20 describes control of the high-speed CAN module,
mode, slew rate, and wake-up.
Table 20. CAN Register
CAN
R/W
D3
D2
D1
D0
$010b
W
CANCLR
R
CANWU
SC1
CAN-F
SC0
CAN-UF
MODE
THERM-CUR
Reset Value
–
0
0
0
1
Reset Condition
–
(Write)⁽⁵⁷⁾
POR
POR
POR
NR2N, STB2N
Notes
57. See Table 13, page 47, for definitions of reset conditions.
Table 21. CANCLR Control Bits
Logic
Description
0
No effect.
1
Re-enables CAN driver after TXD permanent dominant or RXD permanent recessive failure occurred. Failure
recovery conditions must occur to re-enable.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33742
49