33742_08 Datasheet, PDF (17/70 Pages) Freescale Semiconductor, Inc – System Basis Chip with Enhanced High Speed CAN Transceiver

ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 6. Dynamic Electrical Characteristics
Characteristics noted under conditions 4.75V ≤ V2 ≤ 5.25V, 5.5V ≤ V_SUP ≤ 18V, and -40°C ≤ T_A ≤ 125°C. Typical values noted
reflect the approximate parameter mean at T_A = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
DIGITAL INTERFACE TIMING (SCLK, CS, MOSI, MISO)⁽²⁹⁾
SPI Operation Frequency
SCLK Clock Period
SCLK Clock High Time
SCLK Clock Low Time
Falling Edge of CS to Rising Edge of SCLK
Falling Edge of SCLK to Rising Edge of CS
MOSI to Falling Edge of SCLK
Falling Edge of SCLK to MOSI
MISO Rise Time⁽³⁰⁾
C_L = 220pF
MISO Fall Time⁽³⁰⁾
C_L = 220pF
f _REQ
0.25
—
4.0
MHz
t _PCLK
250
—
N/A
ns
t _WSCLKH
125
—
N/A
ns
t _WSCLKL
125
—
N/A
ns
t _LEAD
100
—
N/A
ns
t _LAG
100
—
N/A
ns
t _SISU
40
—
N/A
ns
t _SIH
40
—
N/A
ns
t _RSO
ns
—
25
50
t _FSO
ns
—
25
50
Time from Falling or Rising Edges of CS
MISO Low-impedance
MISO High-impedance
ns
t _SOEN
—
—
50
t _SODIS
—
—
50
Time from Rising Edge of SCLK to MISO Data Valid
0.2 V_DD ≤ MISO ≥ 0.8 V_DD, C_L = 200pF
t _VALID
ns
—
—
50
STATE MACHINE TIMING (CS, SCLK, MOSI, MISO, WDOG, INT)
Delay Between CS LOW-to-HIGH Transition (at End of SPI Stop Command)
and Stop mode Activation⁽³¹⁾
t _CS-STOP
18
—
μs
34
Interrupt Low-level Duration
Stop Mode
Internal Oscillator Frequency⁽³²⁾
Notes
29. See Figure 7, SPI Timing Diagram, page 22.
30. Not production tested. Guaranteed by design.
31. Not production tested. Guaranteed by design. Detected by V2 OFF.
32. f_OSC is indirectly measured (1.0ms reset) and trimmed.
t _INT
f _OSC
μs
7.0
10
13
—
100
—
kHz
Analog Integrated Circuit Device Data
Freescale Semiconductor
33742
17