33742_08 Datasheet, PDF (20/70 Pages) Freescale Semiconductor, Inc – System Basis Chip with Enhanced High Speed CAN Transceiver

ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 6. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 4.75V ≤ V2 ≤ 5.25V, 5.5V ≤ V_SUP ≤ 18V, and -40°C ≤ T_A ≤ 125°C. Typical values noted
reflect the approximate parameter mean at T_A = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
STATE MACHINE TIMING (CS, SCLK, MOSI, MISO, WDOG, INT) (CONTINUED)
Delay Between SPI and CAN Normal mode⁽³⁴⁾
Normal mode⁽³⁵⁾
t _{S-CAN_N}
μs
—
—
10
Delay Between SPI and CAN Sleep Mode⁽³⁴⁾
Normal mode ⁽³⁵⁾
t _{S-CAN_S}
μs
—
—
10
Delay Between CS Wake-up (CS LOW to HIGH) and Device in Normal
t _W-CS
μs
Request mode (VDD ON and RST HIGH)
Stop mode
15
40
90
Delay Between CS Wake-up (CS LOW to HIGH) and First Accepted SPI
t _W-SPI
μs
Command
Device in Stop mode After Wake-up
90
—
N/A
Delay Between INT Pulse and First SPI Command Accepted
Device in Stop mode After Wake-up
t _S-1STSPI
20
μs
—
N/A
Delay Between Two SPI Messages Addressing the Same Register
OUTPUT PIN (VDD)
t _2SPI
25
—
—
μs
Reset Delay Time
Measured at 50% of Reset Signal
I_DD Over-current to Wake-up Deglitcher Time⁽³⁵⁾
t_D
μs
4.0
—
30
t_IDD-DGLT
40
55
75
μs
OUTPUT PIN (RST)
Reset Duration After VDD HIGH
33742
33742S
INPUT PINS (L0, L1, L2, AND L3)
ms
t _RSTDUR
12
15
18
t _RSTDURS
3.0
3.5
4.0
Wake-up Filter Time
t _WUF
8.0
20
38
μs
Notes
34. Delay starts at falling edge of clock cycle #8 of the SPI command and start of “Turn ON” or “Turn OFF” of HS or V2.
35. Guaranteed by design; it is not production tested.
33742
20
Analog Integrated Circuit Device Data
Freescale Semiconductor