33742_08 Datasheet, PDF (24/70 Pages) Freescale Semiconductor, Inc – System Basis Chip with Enhanced High Speed CAN Transceiver

FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
the state of CANH and CANL is reported through RXD output.
A 60Ω termination resistor is connected between CANH and
CANL pins.
SERIAL DATA CLOCK (SCLK)
SCLK is the Serial Data Clock input pin of the serial
peripheral interface.
MASTER IN SLAVE OUT (MISO)
MISO is the Master In Slave Out pin of the serial peripheral
interface. Data is sent from the SBC to the microcontroller
through the MISO pin.
MASTER OUT SLAVE IN (MOSI)
MOSI is the Master Out Slave In pin of the serial peripheral
interface. Control data from a microcontroller is received
through this pin.
CHIP SELECT (CS)
CS is the Chip Select pin of the serial peripheral interface.
When this pin is LOW, the SPI port of the device is selected.
WATCHDOG OUTPUT (WDOG)
The Watchdog output pin is asserted LOW to flag that the
software watchdog has not been properly triggered.
33742
24
Analog Integrated Circuit Device Data
Freescale Semiconductor