33742_08 Datasheet, PDF (66/70 Pages) Freescale Semiconductor, Inc – System Basis Chip with Enhanced High Speed CAN Transceiver

ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 2.0)
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 2.0)
Introduction
This thermal addendum is provided as a supplement to the MC33742
technical datasheet. The addendum provides thermal performance
information that may be critical in the design and development of system
applications. All electrical, application, and packaging information is
provided in the data sheet.
Packaging and Thermal Considerations
The MC33742 is offered in a 28 pin SOICW exposed pad, single die
package. There is a single heat source (P), a single junction temperature
(T_J), and thermal resistance (R_θJA).
T_J = _RθJA . _P
The stated values are solely for a thermal performance comparison of
one package to another in a standardized environment. This methodology
is not meant to and will not predict the performance of a package in an
application-specific environment. Stated values were obtained by
measurement and simulation according to the standards listed below.
33742DW
33742EG
28-PIN
SOICW
DW SUFFIX
EG SUFFIX (PB-FREE)
98ASB42345B
28-PIN SOICW
Note For package dimensions, refer to
the 33742 data sheet.
Standards
Table 43. Thermal Performance Comparison
Thermal Resistance
[°C/W]
R_θJA(1), ⁽²⁾
41
R_θJB(2), ⁽³⁾
10
R_θJA(1), ⁽⁴⁾
68
R_θJC⁽⁵⁾
220
Notes:
1. Per JEDEC JESD51-2 at natural convection, still air
condition.
2. 2s2p thermal test board per JEDEC JESD51-7.
3. Per JEDEC JESD51-8, with the board temperature on the
center trace near the center lead.
4. Single layer thermal test board per JEDEC JESD51-3.
5. Thermal resistance between the die junction and the
package top surface; cold plate attached to the package top
surface and remaining surfaces insulated.
1.0
0.2
1.0
0.2
* All measurements
are in millimeters
28 Pin SOICW
1.27 mm Pitch
16.0 mm x 7.5 mm Body
Figure 38. Surface Mount for SOIC Wide Body
non-Exposed Pad
33742
66
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Freescale Semiconductor