33742_08 Datasheet, PDF (60/70 Pages) Freescale Semiconductor, Inc – System Basis Chip with Enhanced High Speed CAN Transceiver

TYPICAL APPLICATIONS
POWER-UP AND VDD GOING LOW WITH SLEEP MODE AS DEFAULT LOW POWER MODE IS SELECTED
The first part of Figure 35 is identical to Figure 34. If VDD is pulled below the VDD under-voltage reset (typ 4.6V), say by an
over-current or short-circuit (for instance, short to 4.0V), and if the low power mode previously selected was Sleep mode and if
the BATFAIL flag has been cleared, the 33742 enters in Reset mode for a time period of 100ms. The WDOG pin stays HIGH,
but the high level (VOH) follows VDD level. The RST and INT pins are low. After 100ms the 33742 goes into Sleep mode, and
the VDD and V2 are off.
Figure 35 shows an example wherein VDD is shorted to 4.0V, and after 100ms the 33742 enters Sleep mode.
.
Under-voltage at VDD
VDD
Watchdog Refresh
SPI (CS)
100ms
WD
RST
INT
Reset mode
SBC in
Reset
mode
SBC in Normal Request
& Reset modes
Reset each 350ms
SBC in Normal
mode
SBC in Sleep mode
SBC in Reset mode for
100ms, then enter
Sleep mode
Figure 35. Under-voltage at VDD. Sleep mode selected.
CANH
CANH (33742)
CH
R5
CAN L
CAN Connector
CANL (33742)
CL
Legend
R5: 60Ω
CL, CH: 220pF
Figure 36. CAN Bus Standard Termination
CANH
CANL
CAN Connector
CANH (33742)
R6
CH
R7
CANL (33742)
CL
CS
Legend
R6, R7: 30Ω
CL, CH: 220pF
CS: > 470pF
Figure 37. CAN Bus Split Termination
33742
60
Analog Integrated Circuit Device Data
Freescale Semiconductor