33742_08 Datasheet, PDF (51/70 Pages) Freescale Semiconductor, Inc – System Basis Chip with Enhanced High Speed CAN Transceiver

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 25. HSON Control Bits
Logic
HS State
0
HS OFF, in Normal and Standby modes.
1
HS ON, in Normal and Standby modes.⁽⁶⁰⁾
Notes
60. When HS is turned OFF due to an over-temperature condition, it can be turned ON again by setting the appropriate control bit to 1. Error
bits are latched in the IOR register.
Table 26. Input / Output Register Status Bits
Name
Logic
0
V2LOW
1
0
HSOT
1
0
VSUPLOW
1
0
DEBUG
1
Description
V_2LTH > 4.0V.
V_2LTH < 4.0V.
No HS over-temperature.
HS over-temperature.
V_BF(EW) > 5.8V.
V_BF(EW) < 5.8V.
SBC not in Debug mode.
SBC accepts command to go to Debug modes (no Watchdog).
WAKE-UP REGISTER (WUR)
Tables 27 through 29 contain the Wake-up Register information. Local wake-up inputs L0 : L3 can be used in both Normal and
Standby modes as port expander, as well as for waking up the SBC from Sleep or Stop modes (Table 27).
Table 27. Wake-Up Register
WUR
R/W
D3
W
$100b
R
Reset Value
–
Reset Condition (Write)⁽⁶¹⁾
–
LCTR3
L3WU
0
Notes
61. See Table 13, page 47, for definitions of reset conditions.
Wake-up inputs can be configured by pair. L0 and L1 can
be configured together, and L1 and L2, and L2 and L3 can be
configured together (Table 28).
D2
D1
LCTR2
L2WU
0
LCTR1
L1WU
0
POR, NR2R, N2R, STB2R, STO2R
D0
LCTR0
L0WU
0
Analog Integrated Circuit Device Data
Freescale Semiconductor
33742
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