33742_08 Datasheet, PDF (52/70 Pages) Freescale Semiconductor, Inc – System Basis Chip with Enhanced High Speed CAN Transceiver

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 28. Wake-up Register Control Bits
LCTR3
LCTR2
LCTR1
x
x
0
x
x
0
x
x
1
x
x
1
0
0
x
0
1
x
1
0
x
1
1
x
x = Don’t care.
LCTR0
0
1
0
1
x
x
x
x
L0 L1 : L1 L2 Config
Inputs Disabled
High Level Sensitive
Low Level Sensitive
Both Level Sensitive
–
L2 L3 : L3 L4 Config
–
Inputs Disabled
High Level Sensitive
Low Level Sensitive
Both Level Sensitive
Table 29. Wake-up Register Status Bits ⁽⁶²⁾
Name
Logic
Description
L3WU
L2WU
L1WU
0 or 1
0 or 1
0 or 1
If bit = 1, wake-up occurred from Sleep or Stop modes; if bit = 0, no wake-up has
occurred.
When device is in Normal or Standby mode, bit reports the State on Lx pin (LOW
or HIGH) (0 = Lx LOW, 1 = Lx HIGH)
L0WU
0 or 1
Notes
62. WUR status bits have two functions. After SBC wake-up, they indicate the wake-up source; for example, L2WU set at logic [1] if wake-
up source is L2 input. After SBC wake-up and once the WUR register has been read, status bits indicate the real-time state of the Lx
inputs (1 = Lx is above threshold, 0 = Lx input is below threshold). If after a wake-up from Lx input a watchdog timeout occurs before the
first reading of the WUR register, the LxWU bits are reset. This can occur only if the SBC was in Stop mode.
TIMING REGISTER (TIM1 / 2)
Tables 30 through 34 contain the Timing Register information. The TIM register is composed of two sub registers:
• TIM1—Controls the watchdog timing selection as well as either the watchdog window or the watchdog timeout option
(Figure 28 and Figure 29, respectively). TIM1 is selected when bit D3 is 0 (Table 30). Watchdog timing characteristics are
described in Table 31.
• TIM2—Selects an appropriate timing for sensing the wake-up circuitry or cyclically supplying devices by switching the HS on
or off. TIM2 is selected when bit D3 is 1 (Table 32). Figure 30, page 54, describes HS operation when cyclic sense is selected
Cyclic sense timing characteristics are described in Table 34, page 54.
Both subregisters also report the CANL and TXD diagnostics.
Table 30. TIM1 Timing and CANL Failure Diagnostic Register
TIM1
R/W
D3
D2
$101b
W
0
R
CANL2VDD
WDW
CANL2BAT
Reset Value
–
–
0
Reset Condition
–
–
POR, RESET
(Write)⁽⁶³⁾
Notes
63. See Table 13, page 47, for definitions of reset conditions.
D1
WDT1
CANL2GND
0
POR, RESET
D0
WDT0
TXPD
0
POR, RESET
33742
52
Analog Integrated Circuit Device Data
Freescale Semiconductor