33742_08 Datasheet, PDF (47/70 Pages) Freescale Semiconductor, Inc – System Basis Chip with Enhanced High Speed CAN Transceiver

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS
SPI INTERFACE AND REGISTER DESCRIPTION
DATA FORMAT DESCRIPTION
Figure 27 illustrates an 8-bit byte corresponding to the
8 bits in a SPI register. The first three bits are used to identify
the internal SBC register address. Bit 4 is a read/write bit.
The last four bits are data sent from the MCU to the SBC or
read back from the 33742 to the MCU.
The state of the MISO has no significance during the write
operation. However, during a read operation the final four bits
of MISO have meaning; namely, they contain the content of
the accessed register.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MISO
MOSI
A2 A1 A0 R/W D3 D2 D1 D0
Address
Data
Note Read operation: R/W bit = logic [0]
: Write operation: R/W = logic [1]
Figure 27. Data Format Description.
Table 13. Possible Reset Conditions
Condition
Name
Definition
33742 Reset
33742 Mode
Transition
33742 Mode
POR
NR2R
NR2N
NR2STB
N2R
STB2R
STO2R
STO2NR
RESET
Power-ON Reset
Normal Request to Reset mode
Normal Request to Normal mode
Normal Request to Standby mode
Normal to Reset mode
Standby to Reset mode
Stop to Reset mode
Stop to Normal Request
33742S in Reset mode
REGISTER DESCRIPTIONS
The following tables in this section describe the SPI
register list and register bit meaning. Register reset values
are also described, along with the reset condition. A reset
condition is the condition causing the bit to be set at the reset
value.
Table 14. List of Registers
Register Address
Formal Name
and Link
Write
Comment and Use
Read
MCR
RCR
CAN
$000
$001
$010
Mode Control Register (MCR) Selection for Normal, Standby, Sleep,
on page 48
Stop, and Debug modes
BATFAIL, general failure, VDD pre-
warning, and Watchdog flag
Reset Control Register (RCR) ^{Configuration for reset voltage level, CAN Sleep and Stop modes}
on page 49
CAN Register (CAN) on page ^{CAN slew rate, Sleep and Wake-up}
CAN wake-up and CAN failure status bits
49
enable/disable modes, drive enable after
failure
IOR
WUR
TIM
LPC
$011
$100
$101
$110
Input / Output Register (IOR) ^{HS (high side switch) control in Normal HS over-temperature bit, VSUP, and V2}
on page 50
and Standby mode
LOW status
on page 51
Control of wake-up input polarity
Wake-up input and real time Lx input
state
Timing Register (TIM1/2) on ^{• TIM1: Watchdog timing control, Watch- CANL and TXD failure reporting}
page 52
dog Window (WDW) or Watchdog Tim-
eout (WTO) mode
• TIM2: Cyclic Sense and Forced Wake-
up timing selection
Low Power Control Register ^{Control HS periodic activation in Sleep CANH and RXD failure reporting}
(LPC) on page 54
and Stop modes, Forced Wake-up mode
activation, CAN-INT mode selection
INTR
$111
Interrupt Register (INTR) on ^{Enable or Disable of Interrupts}
page 56
Interrupt source
Analog Integrated Circuit Device Data
Freescale Semiconductor
33742
47