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33742_08 Datasheet, PDF (33/70 Pages) Freescale Semiconductor, Inc – System Basis Chip with Enhanced High Speed CAN Transceiver
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Watchdog: Timeout OR VDD Low
Watchdog: Timeout & Nostop &!BATFAIL
Reset
Power
Down
Reset Counter (3.4 ms)
Expired
2
SPI: Standby and
Watchdog Trigger
1
Normal Request 3
Standby
1
Watchdog:
VDD Low OR Watchdog:
Timeout 350 ms & Nostop
Timeout OR V
DD Low (44)
1
2
Stop
4
to
SPI: SHtoipgh&TCraSnLsToirtwiiogWngaetrchdog:
Normal
SPI: Stop & CS
LOW to HIGH
Watchdog: Timeout OR VDD Low
Transition
1
Wake-Up
(VDD High Temperature OR [VDD Low > 100 ms & VSUP > BFew]) & Nostop &!BATFAIL
Sleep
1 2 3 4 Denotes priority
State Machine Description
Nostop = Nostop bit = 1
! Nostop = Nostop bit = 0
BATFAIL = Batfail bit = 1
! BATFAIL = Batfail bit = 0
VDD Over-temperature = VDD thermal shutdown occurs
VDD LOW = VDD below reset threshold
VDD LOW > 100 ms = VDD below reset threshold for more than 100 ms
Watchdog: Trigger = TIM1 subregister write operation
VSUP > BFew = VSUP > Battery Fail Early Warning (6.1 V typical)
Watchdog: Timeout = TIM1 register not written before watchdog timeout period
expired, or watchdog written in incorrect time window if watchdog window
selected (except Stop mode). In Normal Request mode, timeout is 355 ms
p2.2 (350 ms p3) ms.
SPI: Sleep = SPI write command to MCR register, data sleep
SPI: Stop = SPI write command to MCR register, data stop
SPI: Normal = SPI write command to MCR register, data normal
SPI: Standby = SPI write command to MCR register, data standby
Notes
43. These two SPI commands must be sent consecutively in this sequence.
44. If watchdog activated.
Figure 13. SBC State Diagram (Not Valid in Debug Modes)
Power-Up
Reset
Operation after power-up if no trigger appears
Operation after reset of BATFAIL if no trigger appears
Normal
Request
No
Trigger
Yes
Normal
Yes
No
Batfail
No
Yes
No Stop
Sleep
Figure 14. Operation After SBC Power-Up
Analog Integrated Circuit Device Data
Freescale Semiconductor
33742
33