33742_08 Datasheet, PDF (48/70 Pages) Freescale Semiconductor, Inc – System Basis Chip with Enhanced High Speed CAN Transceiver

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
MODE CONTROL REGISTER (MCR)
Tables 15 through 17 describes the various Mode Control Registers.
Table 15. Mode Control Register
MCR
R/W
D3
D2
$000b
W
–
R
BATFAIL⁽⁵²⁾
MCTR2
VDDTEMP
Reset Value
–
–
Reset Condition (Write)⁽⁵³⁾
–
–
0
POR, RESET
Notes
52. BATFAIL bit cannot be set by SPI. BATFAIL is set when VSUP falls below 3.0V.
53. See Table 13 page 47, for definitions of reset conditions
D1
MCTR1
GFAIL
0
POR, RESET
D0
MCTR0
WDRST
0
POR, RESET
Table 16. Mode Control Register Control Bits
MCTR MCTR MCTR
2
1
0
33742S Mode
Description
0
0
0
Enter/Exit Debug ^{To enter/exit Debug Mode, refer to detailed description in Debug Mode: Hardware and}
Mode
Software Debug with the 33742, page 34.
0
0
1
Normal
–
0
1
0
Standby
–
0
1
1
Stop, Watchdog
–
OFF⁽⁵⁴⁾
0
1
1
Stop, Watchdog
–
ON⁽⁵⁴⁾
1
0
0
Sleep⁽⁵⁵⁾
–
1
0
1
Normal
No Watchdog running. Debug mode.
1
1
0
Standby
1
1
1
Stop
Notes
54. Watchdog ON or OFF depends on RCR bit D3.
55. Before entering Sleep mode, BATFAIL bit in MCR must be previously cleared (MCR read operation), and NOSTOP bit in RCR must be
previously set to logic [1].
Table 17. Mode Control Register Status Bits
Name
Logic
0
BATFAIL
1
0
VDDTEMP
1
0
GFAIL
1
0
WDRST
1
Description
VSUP was not below V_BF.
VSUP has been below V_BF.
No over-temperature pre-warning.
Temperature pre-warning on VDD regulator (bit latched).
No failure.
CAN Failure or HS over-temperature or V2 low.
No watchdog reset occurred.
Watchdog reset occurred.
33742
48
Analog Integrated Circuit Device Data
Freescale Semiconductor