33742_08 Datasheet, PDF (56/70 Pages) Freescale Semiconductor, Inc – System Basis Chip with Enhanced High Speed CAN Transceiver

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
INTERRUPT REGISTER (INTR)
Tables 40 through 42 contain the Interrupt Register information. The INTR register allows masking or enabling the interrupt
source. A read operation identifies the interrupt source. Table 42 provides status bit information. The status bits of the INTR
register content are copies of the IOR, CAN, TIM, and LPC registers status content. To clear the Interrupt Register bits, the IOR,
CAN, TIM, and/or LPC registers must be cleared (read register) and the recovery condition must occur. Errors bits are latched
in the CAN register and the IOR register.
Table 40. Interrupt Register
INTR
$111b
R/W
W
R
D3
VSUPLOW
VSUPLOW
D2
HSOT-V2LOW⁽⁶⁷⁾
HSOT
D1
V1TEMP
V1TEMP
D0
CANF
CANF
Reset Value
–
0
0
0
0
Reset Condition
–
(Write)⁽⁶⁸⁾
POR, RST
POR, RST
POR, RST
POR, RST
Notes
67. If only HSOT - V2LOW interrupt is selected (only bit D2 set in INTR register), reading INTR register bit D2 leads to two possibilities:
1. Bit D2 = 1: Interrupt source is HSOT.
2. Bit D2 = 0: Interrupt source is V2LOW.
HSOT and V2LOW bits status are available in the IOR register.
68. See Table 13, page 47, for definitions of reset conditions.
Table 41. Interrupt Register Control Bits
Name
Description
CANF
Mask bit for CAN failures.
VDDTEMP
Mask bit for VDD medium temperature
(pre-warning).
HSOT - V2LOW
Mask bit for HS over-temperature AND V_2LTH < 4.0V.
VSUPLOW
Mask bit for V_BF(EW) < 5.8V.
When the mask bit is set, the INT pin goes LOW if the appropriate condition occurs. Upon a wake-up condition from Stop mode
due to over-current detection (I_DDS-WU1 or I_DDS-WU2), an INT pulse is generated; however, INTR register content remains at 0000
(not bit set into the INTR register).
Table 42. Interrupt Register Status Bits
Name
Logic
0
VSUPLOW
1
0
HSOT
1
0
VDDTEMP
1
0
CANF
1
Description
No V_BF(EW) < 5.8V.
V_BF(EW) < 5.8V.
No HS over-temperature.
HS over-temperature.
No VDD medium temperature (pre-warning).
VDD medium temperature (pre-warning).
No CAN failure.
CAN failure.
33742
56
Analog Integrated Circuit Device Data
Freescale Semiconductor