33742_08 Datasheet, PDF (54/70 Pages) Freescale Semiconductor, Inc – System Basis Chip with Enhanced High Speed CAN Transceiver

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Cyclic Sense Timing,
ON Time
HS ON
HS ^{Cyclic Sense Timing, OFF Time}
HS OFF
10μs
Sample
Lx Sampling Point
time
Figure 30. HS Operation When Cyclic Sense Is Selected
Table 34. TIM2 Control Bits
CSP2
CSP1
CSP0
Cyclic Sense Timing (ms) Parameter
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
4.6
9.25
18.5
37
74
95.5
191
388
Cyclic Sense/FWU Timing 1
Cyclic Sense/FWU Timing 2
Cyclic Sense/FWU Timing 3
Cyclic Sense/FWU Timing 4
Cyclic Sense/FWU Timing 5
Cyclic Sense/FWU Timing 6
Cyclic Sense/FWU Timing 7
Cyclic Sense/FWU Timing 8
LOW POWER CONTROL REGISTER (LPC)
Tables 35 through 39 contain the Low Power Control Register information. The LPC register controls:
• The state of HS in Stop and Sleep modes (HS permanently OFF or HS cyclic).
• Enable or disable of the forced wake-up function (SBC automatic wake-up after time spent in Sleep or Stop modes; time is
defined by the TIM2 sub register).
• Enable or disable the sense of the wake-up inputs (Lx) at the sampling point of the Cyclic Sense period (LX2HS bit). (Refer to
Reset Control Register (RCR) on page 49 for details of the LPC register setup required for proper cyclic sense or direct wake-
up operation.
The LPC register also reports the CANH and RXD diagnostic.
Table 35. Low Power Control Register
LPC
R/W
D3
$110b
W
LX2HS
R
CANH2VDD
Reset Value
Reset Condition
(Write)⁽⁶⁵⁾
–
0
–
POR, NR2R, N2R,
STB2R, STO2R
Notes
65. See Table 13, page 47, for definitions of reset conditions.
D2
FWU
CANH2BAT
0
POR, NR2R, N2R,
STB2R, STO2R
D1
CAN-INT
CANH2GND
0
POR, NR2R, N2R,
STB2R, STO2R
D0
HSAUTO
RXPR
0
POR, NR2R, N2R,
STB2R, STO2R
33742
54
Analog Integrated Circuit Device Data
Freescale Semiconductor