33742_08 Datasheet, PDF (58/70 Pages) Freescale Semiconductor, Inc – System Basis Chip with Enhanced High Speed CAN Transceiver

TYPICAL APPLICATIONS
VOLTAGE REGULATOR
The SBC contains two 5.0V regulators: a V1 regulator,
fully integrated and protected, and a V2 regulator, which
operates with an external ballast transistor.
VDD REGULATOR
The VDD regulator provides 5.0V output, 2.0% accuracy
with current capability of 200mA max. It requires external
decoupling and stabilizing capacitors. The minimum
recommended values are as follows:
• C4: 100nF
• C3: 10μF < C3 <22μF, ESR < 1.0Ω or
• C3: 22μF < C3 <47μF, ESR < 5.0Ω or
• C3: ≥47μF, ESR < 10Ω
V2 REGULATOR: OPERATING WITH EXTERNAL
BALLAST TRANSISTOR
The V2 regulator is a tracking regulator of the VDD output.
Its accuracy relative to VDD is ±1.0%. It requires external
decoupling and stabilizing capacitors.
V_PWR
No Connect
33742
V2CTRL
V2
VSUP
C1 C2
VDD
RST
The recommended value are as follows:
• 22μF, ESR < 5.0Ω
• 47μF, ESR < 10Ω
The V2 pin has two functions: it is a sense input for the V2
regulator and is a 5.0V power supply input to the CAN
interface.
With respect to ballast transistor selection, either PNP or
PMOS transistors may be used. A resistor between base and
emitter (or source and drain) is necessary to ensure proper
operation and optimized performances. Recommended
bipolar transistor is MJD32C.
V2 REGULATOR: OPERATION WITHOUT
BALLAST TRANSISTOR
The external ballast transistor is optional. If the application
does not requires more than the maximum output current
capability of the VDD regulator, then the ballast transistor can
be omitted. The thermal aspects must be analyzed as well.
The electrical connection is illustrated in Figure 32.
C3 C4
V_DD
RESET
MCU
Components List
C1: 22μF
C2: 100nF
C3: >10μF
C4: 100nF
Figure 32. V2 Regulator Electrical Connection
FAILURE ON VDD, WDOG, RESET, AND INT PINS
The paragraphs below describe the behavior of the device
and of the INT, RST, and WDOG pins at power-up and under
failure of the VDD regulator.
POWER-UP AND SBC ENTERING NORMAL
OPERATION
After power-up the 33742 enters Normal Request mode
(CAN interface is in TXRX mode): VDD is on and V2 is off.
After 350ms if no watchdog is written (no TIM1 register
write), a reset occurs and the 33742 returns to Normal
Request mode. During this sequence WDOG is active (low
level).
Once watchdog is written, the 33742 goes to Normal
mode: VDD is still on and V2 turns on, WDOG is no longer
active, and the RST pin is HIGH. If watchdog is not refreshed,
the 33742 generates a reset and returns to Normal Request
mode. Figure 33, page 59, illustrates the operation.
33742
58
Analog Integrated Circuit Device Data
Freescale Semiconductor